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[/] [ofdm/] [trunk/] [vhdl/] [txrx.vhd] - Diff between revs 3 and 8

Rev 3	Rev 8
Line 1...	Line 1...
`library IEEE;`	`library IEEE;`
`use IEEE.STD_LOGIC_1164.ALL;`	`use IEEE.STD_LOGIC_1164.ALL;`
`use IEEE.STD_LOGIC_ARITH.ALL;`	`use IEEE.STD_LOGIC_ARITH.ALL;`
`use IEEE.STD_LOGIC_UNSIGNED.ALL;`	`use IEEE.STD_LOGIC_UNSIGNED.ALL;`

`-- Uncomment the following lines to use the declarations that are`
`-- provided for instantiating Xilinx primitive components.`
`--library UNISIM;`
`--use UNISIM.VComponents.all;`

`entity txrx is`	`entity txrx is`
`Port ( clk : in std_logic;`	`Port ( clk : in std_logic;`
`rst : in std_logic;`	`rst : in std_logic;`
`Output_enable : in std_logic;`	`Output_enable : in std_logic;`
`mem_block : in std_logic;`	`mem_block : in std_logic;`
Line 68...	Line 63...
`mem_ready <= '1';`	`mem_ready <= '1';`
`end case;`	`end case;`
`end if;`	`end if;`
`end process;`	`end process;`


`process(clk,rst)`	`process(clk,rst)`
`begin`	`begin`
`if rst = '1' then`	`if rst = '1' then`
`st <= s0;`	`st <= s0;`
`elsif clk'event and clk='1' then`	`elsif clk'event and clk='1' then`
Line 92...	Line 86...
`end case;`	`end case;`
`end if;`	`end if;`
`end process;`	`end process;`

`end interface;`	`end interface;`

`No newline at end of file`	`No newline at end of file`