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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy, desAc, desOv);
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module oc8051_alu (clk, resetn, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy, desAc, desOv);
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//
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//
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// op_code (in) operation code [oc8051_decoder.alu_op -r]
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// op_code (in) operation code [oc8051_decoder.alu_op -r]
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// src1 (in) first operand [oc8051_alu_src1_sel.des]
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// src1 (in) first operand [oc8051_alu_src1_sel.des]
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// src2 (in) second operand [oc8051_alu_src2_sel.des]
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// src2 (in) second operand [oc8051_alu_src2_sel.des]
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// src3 (in) third operand [oc8051_alu_src3_sel.des]
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// src3 (in) third operand [oc8051_alu_src3_sel.des]
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// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
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// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
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// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
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// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
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// desOv (out) Overflow output [oc8051_psw.ov_in]
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// desOv (out) Overflow output [oc8051_psw.ov_in]
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//
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//
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input srcCy, srcAc, bit_in, clk, rst; input [3:0] op_code; input [7:0] src1, src2, src3;
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input srcCy, srcAc, bit_in, clk, resetn; input [3:0] op_code; input [7:0] src1, src2, src3;
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output desCy, desAc, desOv;
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output desCy, desAc, desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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output [7:0] des1_r;
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output [7:0] des1_r;
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reg desCy, desAc, desOv;
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reg desCy, desAc, desOv;
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//da
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//da
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//
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//
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reg da_tmp;
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reg da_tmp;
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//reg [8:0] da1;
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//reg [8:0] da1;
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oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
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oc8051_multiply oc8051_mul1(.clk(clk), .resetn(resetn), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
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oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
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oc8051_divide oc8051_div1(.clk(clk), .resetn(resetn), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
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/* Add */
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/* Add */
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assign add1 = {1'b0,src1[3:0]};
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assign add1 = {1'b0,src1[3:0]};
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assign add2 = {1'b0,src2[3:0]};
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assign add2 = {1'b0,src2[3:0]};
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assign add3 = {3'b000,srcCy};
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assign add3 = {3'b000,srcCy};
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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ides1_r <= #1 8'h0;
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ides1_r <= #1 8'h0;
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end else begin
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end else begin
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ides1_r <= #1 ides1;
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ides1_r <= #1 ides1;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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desCy <= #1 1'b0;
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desCy <= #1 1'b0;
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desAc <= #1 1'b0;
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desAc <= #1 1'b0;
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desOv <= #1 1'b0;
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desOv <= #1 1'b0;
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des1 <= #1 8'h00;
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des1 <= #1 8'h00;
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des2 <= #1 1'h00;
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des2 <= #1 1'h00;
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