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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//
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//
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_b_register (clk, rst, bit_in, data_in, wr, wr_bit,
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module oc8051_b_register (clk, resetn, bit_in, data_in, wr, wr_bit,
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wr_addr, data_out);
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wr_addr, data_out);
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input clk, rst, wr, wr_bit, bit_in;
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input clk, resetn, wr, wr_bit, bit_in;
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input [7:0] wr_addr, data_in;
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input [7:0] wr_addr, data_in;
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output [7:0] data_out;
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output [7:0] data_out;
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reg [7:0] data_out;
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reg [7:0] data_out;
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//
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//
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//writing to b
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//writing to b
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//must check if write high and correct address
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//must check if write high and correct address
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst)
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if (resetn == 1'b0)
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data_out <= #1 `OC8051_RST_B;
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data_out <= #1 `OC8051_RST_B;
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else if (wr) begin
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else if (wr) begin
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if (!wr_bit) begin
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if (!wr_bit) begin
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if (wr_addr==`OC8051_SFR_B)
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if (wr_addr==`OC8051_SFR_B)
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data_out <= #1 data_in;
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data_out <= #1 data_in;
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