| Line 15... |
Line 15... |
//// Author(s): ////
|
//// Author(s): ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
//// v0.0 - Dinesh A, 5th Jan 2017
|
|
//// 1. Active edge of reset changed from High to Low
|
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
| Line 82... |
Line 85... |
//
|
//
|
|
|
`include "top_defines.v"
|
`include "top_defines.v"
|
|
|
|
|
module oc8051_decoder (clk, rst, op_in, op1_c,
|
module oc8051_decoder (clk, resetn, op_in, op1_c,
|
ram_rd_sel_o, ram_wr_sel_o,
|
ram_rd_sel_o, ram_wr_sel_o,
|
bit_addr, wr_o, wr_sfr_o,
|
bit_addr, wr_o, wr_sfr_o,
|
src_sel1, src_sel2, src_sel3,
|
src_sel1, src_sel2, src_sel3,
|
alu_op_o, psw_set, eq, cy_sel, comp_sel,
|
alu_op_o, psw_set, eq, cy_sel, comp_sel,
|
pc_wr, pc_sel, rd, rmw, istb, mem_act, mem_wait,
|
pc_wr, pc_sel, rd, rmw, istb, mem_act, mem_wait,
|
wait_data);
|
wait_data);
|
|
|
//
|
//
|
// clk (in) clock
|
// clk (in) clock
|
// rst (in) reset
|
// resetn (in) reset
|
// op_in (in) operation code [oc8051_op_select.op1]
|
// op_in (in) operation code [oc8051_op_select.op1]
|
// eq (in) compare result [oc8051_comp.eq]
|
// eq (in) compare result [oc8051_comp.eq]
|
// ram_rd_sel (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
|
// ram_rd_sel (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
|
// ram_wr_sel (out) select, whitch address will be send to ram for write [oc8051_ram_wr_sel.sel -r, oc8051_sp.ram_wr_sel -r]
|
// ram_wr_sel (out) select, whitch address will be send to ram for write [oc8051_ram_wr_sel.sel -r, oc8051_sp.ram_wr_sel -r]
|
// wr (out) write - if 1 then we will write to ram [oc8051_ram_top.wr -r, oc8051_acc.wr -r, oc8051_b_register.wr -r, oc8051_sp.wr-r, oc8051_dptr.wr -r, oc8051_psw.wr -r, oc8051_indi_addr.wr -r, oc8051_ports.wr -r]
|
// wr (out) write - if 1 then we will write to ram [oc8051_ram_top.wr -r, oc8051_acc.wr -r, oc8051_b_register.wr -r, oc8051_sp.wr-r, oc8051_dptr.wr -r, oc8051_psw.wr -r, oc8051_indi_addr.wr -r, oc8051_ports.wr -r]
|
| Line 114... |
Line 117... |
// reti (out) return from interrupt [pin]
|
// reti (out) return from interrupt [pin]
|
// rmw (out) read modify write feature [oc8051_ports.rmw]
|
// rmw (out) read modify write feature [oc8051_ports.rmw]
|
// pc_wait (out)
|
// pc_wait (out)
|
//
|
//
|
|
|
input clk, rst, eq, mem_wait, wait_data;
|
input clk, resetn, eq, mem_wait, wait_data;
|
input [7:0] op_in;
|
input [7:0] op_in;
|
|
|
output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3;
|
output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3;
|
output [1:0] psw_set, cy_sel, wr_sfr_o, src_sel2, comp_sel;
|
output [1:0] psw_set, cy_sel, wr_sfr_o, src_sel2, comp_sel;
|
output [2:0] mem_act, src_sel1, ram_rd_sel_o, ram_wr_sel_o, pc_sel, op1_c;
|
output [2:0] mem_act, src_sel1, ram_rd_sel_o, ram_wr_sel_o, pc_sel, op1_c;
|
| Line 1309... |
Line 1312... |
|
|
//
|
//
|
//
|
//
|
// registerd outputs
|
// registerd outputs
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (rst) begin
|
if (resetn == 1'b0) begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
| Line 2750... |
Line 2753... |
end
|
end
|
|
|
|
|
//
|
//
|
// remember current instruction
|
// remember current instruction
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or negedge resetn)
|
if (rst) op <= #1 2'b00;
|
if (resetn == 1'b0) op <= #1 2'b00;
|
else if (state==2'b00) op <= #1 op_in;
|
else if (state==2'b00) op <= #1 op_in;
|
|
|
//
|
//
|
// in case of instructions that needs more than one clock set state
|
// in case of instructions that needs more than one clock set state
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (rst)
|
if (resetn == 1'b0)
|
state <= #1 2'b11;
|
state <= #1 2'b11;
|
else if (!mem_wait & !wait_data) begin
|
else if (!mem_wait & !wait_data) begin
|
case (state) /* synopsys parallel_case */
|
case (state) /* synopsys parallel_case */
|
2'b10: state <= #1 2'b01;
|
2'b10: state <= #1 2'b01;
|
2'b11: state <= #1 2'b10;
|
2'b11: state <= #1 2'b10;
|
| Line 2805... |
Line 2808... |
end
|
end
|
|
|
|
|
//
|
//
|
//in case of writing to external ram
|
//in case of writing to external ram
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (rst) begin
|
if (resetn == 1'b0) begin
|
mem_act <= #1 `OC8051_MAS_NO;
|
mem_act <= #1 `OC8051_MAS_NO;
|
end else if (!rd) begin
|
end else if (!rd) begin
|
mem_act <= #1 `OC8051_MAS_NO;
|
mem_act <= #1 `OC8051_MAS_NO;
|
end else
|
end else
|
casex (op_cur) /* synopsys parallel_case */
|
casex (op_cur) /* synopsys parallel_case */
|
| Line 2823... |
Line 2826... |
`OC8051_MOVC_PC : mem_act <= #1 `OC8051_MAS_CODE;
|
`OC8051_MOVC_PC : mem_act <= #1 `OC8051_MAS_CODE;
|
default : mem_act <= #1 `OC8051_MAS_NO;
|
default : mem_act <= #1 `OC8051_MAS_NO;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (rst) begin
|
if (resetn == 1'b0) begin
|
ram_rd_sel_r <= #1 3'h0;
|
ram_rd_sel_r <= #1 3'h0;
|
end else begin
|
end else begin
|
ram_rd_sel_r <= #1 ram_rd_sel;
|
ram_rd_sel_r <= #1 ram_rd_sel;
|
end
|
end
|
end
|
end
|
