| Line 17... |
Line 17... |
//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 6th Jan 2017
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//// 1. pc_next logic added
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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| Line 1053... |
Line 1055... |
stb_i = 1'b0;
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stb_i = 1'b0;
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bit_addr = 1'b0;
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bit_addr = 1'b0;
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end
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end
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`OC8051_LJMP : begin
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`OC8051_LJMP : begin
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ram_rd_sel = `OC8051_RRS_DC;
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ram_rd_sel = `OC8051_RRS_DC;
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pc_wr = `OC8051_PCW_Y;
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pc_wr = `OC8051_PCW_Y; // Write PC
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pc_sel = `OC8051_PIS_I16;
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pc_sel = `OC8051_PIS_I16; // 16 bit immediate
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comp_sel = `OC8051_CSS_DC;
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comp_sel = `OC8051_CSS_DC; // No Compare
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rmw = `OC8051_RMW_N;
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rmw = `OC8051_RMW_N; // Not Read Modify Command
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stb_i = 1'b0;
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stb_i = 1'b0;
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bit_addr = 1'b0;
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bit_addr = 1'b0;
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end
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end
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`OC8051_MOV_D : begin
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`OC8051_MOV_D : begin
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ram_rd_sel = `OC8051_RRS_D;
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ram_rd_sel = `OC8051_RRS_D;
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| Line 1364... |
Line 1366... |
alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= #1 `OC8051_ALU_NOP;
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wr <= #1 1'b0;
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wr <= #1 1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <= #1 `OC8051_PS_NOT;
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wr_sfr <= #1 `OC8051_WRS_ACC1;
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wr_sfr <= #1 `OC8051_WRS_ACC1;
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end
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end
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/* `OC8051_ACALL :begin
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ram_wr_sel <= #1 `OC8051_RWS_SP;
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src_sel1 <= #1 `OC8051_AS1_PCH;
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src_sel2 <= #1 `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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wr <= #1 1'b1;
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psw_set <= #1 `OC8051_PS_NOT;
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wr_sfr <= #1 `OC8051_WRS_N;
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end
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`OC8051_AJMP : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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wr <= #1 1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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wr_sfr <= #1 `OC8051_WRS_N;
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end
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`OC8051_LCALL :begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
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|
src_sel1 <= #1 `OC8051_AS1_PCH;
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src_sel2 <= #1 `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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wr <= #1 1'b1;
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psw_set <= #1 `OC8051_PS_NOT;
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|
wr_sfr <= #1 `OC8051_WRS_N;
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end*/
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`OC8051_DIV : begin
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`OC8051_DIV : begin
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ram_wr_sel <= #1 `OC8051_RWS_B;
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ram_wr_sel <= #1 `OC8051_RWS_B;
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src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
