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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Jaka Simsic, jakas@opencores.org ////
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//// - Jaka Simsic, jakas@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_int (clk, rst,
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module oc8051_int (clk, resetn,
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wr_addr,
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wr_addr,
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data_in, bit_in,
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data_in, bit_in,
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wr, wr_bit,
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wr, wr_bit,
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//timer interrupts
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//timer interrupts
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tf0, tf1, t2_int,
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tf0, tf1, t2_int,
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Line 87... |
intr, reti, int_vec, ack,
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intr, reti, int_vec, ack,
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//registers
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//registers
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ie, tcon, ip);
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ie, tcon, ip);
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input [7:0] wr_addr, data_in;
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input [7:0] wr_addr, data_in;
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input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
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input wr, tf0, tf1, t2_int, ie0, ie1, clk, resetn, reti, wr_bit, bit_in, ack, uart_int;
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output tr0, tr1, intr;
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output tr0, tr1, intr;
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output [7:0] int_vec,
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output [7:0] int_vec,
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ie,
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ie,
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tcon,
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tcon,
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Line 155... |
assign intr = |int_vec;
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assign intr = |int_vec;
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//
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//
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// IP
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// IP
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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ip <=#1 `OC8051_RST_IP;
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ip <=#1 `OC8051_RST_IP;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
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ip <= #1 data_in;
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ip <= #1 data_in;
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
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ip[wr_addr[2:0]] <= #1 bit_in;
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ip[wr_addr[2:0]] <= #1 bit_in;
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end
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end
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//
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//
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// IE
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// IE
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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ie <=#1 `OC8051_RST_IE;
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ie <=#1 `OC8051_RST_IE;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
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ie <= #1 data_in;
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ie <= #1 data_in;
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
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ie[wr_addr[2:0]] <= #1 bit_in;
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ie[wr_addr[2:0]] <= #1 bit_in;
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end
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end
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//
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//
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// tcon_s
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// tcon_s
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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tcon_s <=#1 4'b0000;
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tcon_s <=#1 4'b0000;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
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tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
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case (wr_addr[2:0]) /* synopsys full_case parallel_case */
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case (wr_addr[2:0]) /* synopsys full_case parallel_case */
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Line 199... |
end
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end
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//
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//
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// tf1 (tmod.7)
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// tf1 (tmod.7)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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tcon_tf1 <=#1 1'b0;
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tcon_tf1 <=#1 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_tf1 <= #1 data_in[7];
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tcon_tf1 <= #1 data_in[7];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
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tcon_tf1 <= #1 bit_in;
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tcon_tf1 <= #1 bit_in;
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Line 217... |
end
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end
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//
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//
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// tf0 (tmod.5)
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// tf0 (tmod.5)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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tcon_tf0 <=#1 1'b0;
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tcon_tf0 <=#1 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_tf0 <= #1 data_in[5];
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tcon_tf0 <= #1 data_in[5];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
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tcon_tf0 <= #1 bit_in;
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tcon_tf0 <= #1 bit_in;
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Line 236... |
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//
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//
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// ie0 (tmod.1)
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// ie0 (tmod.1)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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tcon_ie0 <=#1 1'b0;
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tcon_ie0 <=#1 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_ie0 <= #1 data_in[1];
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tcon_ie0 <= #1 data_in[1];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
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tcon_ie0 <= #1 bit_in;
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tcon_ie0 <= #1 bit_in;
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Line 257... |
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//
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//
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// ie1 (tmod.3)
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// ie1 (tmod.3)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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tcon_ie1 <=#1 1'b0;
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tcon_ie1 <=#1 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_ie1 <= #1 data_in[3];
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tcon_ie1 <= #1 data_in[3];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
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tcon_ie1 <= #1 bit_in;
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tcon_ie1 <= #1 bit_in;
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Line 276... |
end
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end
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end
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end
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//
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//
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// interrupt processing
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// interrupt processing
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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int_vec <= #1 8'h00;
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int_vec <= #1 8'h00;
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int_dept <= #1 2'b0;
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int_dept <= #1 2'b0;
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isrc[0] <= #1 3'h0;
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isrc[0] <= #1 3'h0;
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isrc[1] <= #1 3'h0;
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isrc[1] <= #1 3'h0;
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int_proc <= #1 1'b0;
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int_proc <= #1 1'b0;
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Line 343... |
int_vec <= #1 8'h00;
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int_vec <= #1 8'h00;
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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tf0_buff <= #1 1'b0;
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tf0_buff <= #1 1'b0;
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tf1_buff <= #1 1'b0;
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tf1_buff <= #1 1'b0;
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ie0_buff <= #1 1'b0;
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ie0_buff <= #1 1'b0;
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ie1_buff <= #1 1'b0;
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ie1_buff <= #1 1'b0;
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end else begin
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end else begin
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