| Line 433... |
Line 433... |
`OC8051_RWS_I : wr_addr = ri_r;
|
`OC8051_RWS_I : wr_addr = ri_r;
|
`OC8051_RWS_D : wr_addr = imm_r;
|
`OC8051_RWS_D : wr_addr = imm_r;
|
`OC8051_RWS_SP : wr_addr = sp_w;
|
`OC8051_RWS_SP : wr_addr = sp_w;
|
`OC8051_RWS_D3 : wr_addr = imm2_r;
|
`OC8051_RWS_D3 : wr_addr = imm2_r;
|
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
|
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
|
// default : wr_addr = 2'bxx;
|
default : wr_addr = 2'b00;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0)
|
if (resetn == 1'b0)
|
rd_ind <= #1 1'b0;
|
rd_ind <= 1'b0;
|
else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
|
else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
|
rd_ind <= #1 1'b1;
|
rd_ind <= 1'b1;
|
else
|
else
|
rd_ind <= #1 1'b0;
|
rd_ind <= 1'b0;
|
|
|
always @(wr_sel)
|
always @(wr_sel)
|
if ((wr_sel==`OC8051_RWS_I) || (wr_sel==`OC8051_RWS_SP))
|
if ((wr_sel==`OC8051_RWS_I) || (wr_sel==`OC8051_RWS_SP))
|
wr_ind = 1'b1;
|
wr_ind = 1'b1;
|
else
|
else
|
| Line 468... |
Line 468... |
|
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
iadr_t <= #1 23'h0;
|
iadr_t <= 23'h0;
|
istb_t <= #1 1'b0;
|
istb_t <= 1'b0;
|
imem_wait <= #1 1'b0;
|
imem_wait <= 1'b0;
|
idat_ir <= #1 24'h0;
|
idat_ir <= 24'h0;
|
end else if (mem_act==`OC8051_MAS_CODE) begin
|
end else if (mem_act==`OC8051_MAS_CODE) begin
|
iadr_t <= #1 alu;
|
iadr_t <= alu;
|
istb_t <= #1 1'b1;
|
istb_t <= 1'b1;
|
imem_wait <= #1 1'b1;
|
imem_wait <= 1'b1;
|
end else if (ea_rom_sel && imem_wait) begin
|
end else if (ea_rom_sel && imem_wait) begin
|
imem_wait <= #1 1'b0;
|
imem_wait <= 1'b0;
|
end else if (!imem_wait && istb_t) begin
|
end else if (!imem_wait && istb_t) begin
|
istb_t <= #1 1'b0;
|
istb_t <= 1'b0;
|
end else if (iack_i) begin
|
end else if (iack_i) begin
|
imem_wait <= #1 1'b0;
|
imem_wait <= 1'b0;
|
idat_ir <= #1 idat_i [23:0];
|
idat_ir <= idat_i [23:0];
|
end
|
end
|
end
|
end
|
|
|
/////////////////////////////
|
/////////////////////////////
|
//
|
//
|
| Line 497... |
Line 497... |
assign dadr_o = dadr_ot;
|
assign dadr_o = dadr_ot;
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
dwe_o <= #1 1'b0;
|
dwe_o <= 1'b0;
|
dmem_wait <= #1 1'b0;
|
dmem_wait <= 1'b0;
|
dstb_o <= #1 1'b0;
|
dstb_o <= 1'b0;
|
ddat_o <= #1 8'h00;
|
ddat_o <= 8'h00;
|
dadr_ot <= #1 23'h0;
|
dadr_ot <= 23'h0;
|
end else if (dack_i) begin
|
end else if (dack_i) begin
|
dwe_o <= #1 1'b0;
|
dwe_o <= 1'b0;
|
dstb_o <= #1 1'b0;
|
dstb_o <= 1'b0;
|
dmem_wait <= #1 1'b0;
|
dmem_wait <= 1'b0;
|
end else begin
|
end else begin
|
case (mem_act) /* synopsys full_case parallel_case */
|
case (mem_act) /* synopsys full_case parallel_case */
|
`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr)
|
`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr)
|
dwe_o <= #1 1'b0;
|
dwe_o <= 1'b0;
|
dstb_o <= #1 1'b1;
|
dstb_o <= 1'b1;
|
ddat_o <= #1 8'h00;
|
ddat_o <= 8'h00;
|
dadr_ot <= #1 {7'h0, dptr};
|
dadr_ot <= {7'h0, dptr};
|
dmem_wait <= #1 1'b1;
|
dmem_wait <= 1'b1;
|
end
|
end
|
`OC8051_MAS_DPTR_W: begin // write to external rom: (dptr)=acc
|
`OC8051_MAS_DPTR_W: begin // write to external rom: (dptr)=acc
|
dwe_o <= #1 1'b1;
|
dwe_o <= 1'b1;
|
dstb_o <= #1 1'b1;
|
dstb_o <= 1'b1;
|
ddat_o <= #1 acc;
|
ddat_o <= acc;
|
dadr_ot <= #1 {7'h0, dptr};
|
dadr_ot <= {7'h0, dptr};
|
dmem_wait <= #1 1'b1;
|
dmem_wait <= 1'b1;
|
end
|
end
|
`OC8051_MAS_RI_R: begin // read from external rom: acc=(Ri)
|
`OC8051_MAS_RI_R: begin // read from external rom: acc=(Ri)
|
dwe_o <= #1 1'b0;
|
dwe_o <= 1'b0;
|
dstb_o <= #1 1'b1;
|
dstb_o <= 1'b1;
|
ddat_o <= #1 8'h00;
|
ddat_o <= 8'h00;
|
dadr_ot <= #1 {15'h0, ri};
|
dadr_ot <= {15'h0, ri};
|
dmem_wait <= #1 1'b1;
|
dmem_wait <= 1'b1;
|
end
|
end
|
`OC8051_MAS_RI_W: begin // write to external rom: (Ri)=acc
|
`OC8051_MAS_RI_W: begin // write to external rom: (Ri)=acc
|
dwe_o <= #1 1'b1;
|
dwe_o <= 1'b1;
|
dstb_o <= #1 1'b1;
|
dstb_o <= 1'b1;
|
ddat_o <= #1 acc;
|
ddat_o <= acc;
|
dadr_ot <= #1 {15'h0, ri};
|
dadr_ot <= {15'h0, ri};
|
dmem_wait <= #1 1'b1;
|
dmem_wait <= 1'b1;
|
|
end
|
|
default: begin
|
|
dwe_o <= dwe_o;
|
|
dmem_wait <= dmem_wait;
|
|
dstb_o <= dstb_o;
|
|
ddat_o <= ddat_o;
|
|
dadr_ot <= dadr_ot;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
| Line 551... |
Line 558... |
|
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
idat_cur <= #1 32'h0;
|
idat_cur <= 32'h0;
|
idat_old <= #1 32'h0;
|
idat_old <= 32'h0;
|
end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
|
end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
|
idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i;
|
idat_cur <= ea_rom_sel ? idat_onchip : idat_i;
|
idat_old <= #1 idat_cur;
|
idat_old <= idat_cur;
|
end
|
end
|
|
|
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
cdata <= #1 8'h00;
|
cdata <= 8'h00;
|
cdone <= #1 1'b0;
|
cdone <= 1'b0;
|
end else if (istb_t) begin
|
end else if (istb_t) begin
|
cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0];
|
cdata <= ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0];
|
cdone <= #1 1'b1;
|
cdone <= 1'b1;
|
end else begin
|
end else begin
|
cdone <= #1 1'b0;
|
cdone <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
always @(op_pos or idat_cur or idat_old)
|
always @(op_pos or idat_cur or idat_old)
|
begin
|
begin
|
| Line 657... |
Line 664... |
end
|
end
|
|
|
//
|
//
|
//in case of reti
|
//in case of reti
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) reti <= #1 1'b0;
|
if (resetn == 1'b0) reti <= 1'b0;
|
else if ((op1_o==`OC8051_RETI) & rd & !mem_wait) reti <= #1 1'b1;
|
else if ((op1_o==`OC8051_RETI) & rd & !mem_wait) reti <= 1'b1;
|
else reti <= #1 1'b0;
|
else reti <= 1'b0;
|
|
|
//
|
//
|
// remember inputs
|
// remember inputs
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
op2_buff <= #1 8'h0;
|
op2_buff <= 8'h0;
|
op3_buff <= #1 8'h0;
|
op3_buff <= 8'h0;
|
end else if (rd) begin
|
end else if (rd) begin
|
op2_buff <= #1 op2_o;
|
op2_buff <= op2_o;
|
op3_buff <= #1 op3_o;
|
op3_buff <= op3_o;
|
end
|
end
|
end
|
end
|
|
|
/////////////////////////////
|
/////////////////////////////
|
//
|
//
|
| Line 761... |
Line 768... |
assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
|
assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
op_pos <= #1 3'h0;
|
op_pos <= 3'h0;
|
end else if (pc_wr_r2) begin
|
end else if (pc_wr_r2) begin
|
op_pos <= #1 3'h4;// - op_length;////****??????????
|
op_pos <= 3'h4;// - op_length;////****??????????
|
end else if (inc_pc & rd) begin
|
end else if (inc_pc & rd) begin
|
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
|
op_pos[2] <= op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
|
op_pos[1:0] <= #1 op_pos[1:0] + op_length;
|
op_pos[1:0] <= op_pos[1:0] + op_length;
|
end else if (rd) begin
|
end else if (rd) begin
|
op_pos <= #1 op_pos + {1'b0, op_length};
|
op_pos <= op_pos + {1'b0, op_length};
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// remember interrupt
|
// remember interrupt
|
// we don't want to interrupt instruction in the middle of execution
|
// we don't want to interrupt instruction in the middle of execution
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
int_ack_t <= #1 1'b0;
|
int_ack_t <= 1'b0;
|
int_vec_buff <= #1 8'h00;
|
int_vec_buff <= 8'h00;
|
end else if (intr) begin
|
end else if (intr) begin
|
int_ack_t <= #1 1'b1;
|
int_ack_t <= 1'b1;
|
int_vec_buff <= #1 int_v;
|
int_vec_buff <= int_v;
|
end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0;
|
end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= 1'b0;
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) int_ack_buff <= #1 1'b0;
|
if (resetn == 1'b0) int_ack_buff <= 1'b0;
|
else int_ack_buff <= #1 int_ack_t;
|
else int_ack_buff <= int_ack_t;
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) int_ack <= #1 1'b0;
|
if (resetn == 1'b0) int_ack <= 1'b0;
|
else begin
|
else begin
|
if ((int_ack_buff) & !(int_ack_t))
|
if ((int_ack_buff) & !(int_ack_t))
|
int_ack <= #1 1'b1;
|
int_ack <= 1'b1;
|
else int_ack <= #1 1'b0;
|
else int_ack <= 1'b0;
|
end
|
end
|
|
|
|
|
//
|
//
|
//interrupt buffer
|
//interrupt buffer
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
int_buff1 <= #1 1'b0;
|
int_buff1 <= 1'b0;
|
end else begin
|
end else begin
|
int_buff1 <= #1 int_buff;
|
int_buff1 <= int_buff;
|
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
int_buff <= #1 1'b0;
|
int_buff <= 1'b0;
|
end else if (intr) begin
|
end else if (intr) begin
|
int_buff <= #1 1'b1;
|
int_buff <= 1'b1;
|
end else if (pc_wait)
|
end else if (pc_wait)
|
int_buff <= #1 1'b0;
|
int_buff <= 1'b0;
|
|
|
wire [7:0] pcs_source;
|
wire [7:0] pcs_source;
|
reg [15:0] pcs_result;
|
reg [15:0] pcs_result;
|
reg pcs_cy;
|
reg pcs_cy;
|
|
|
| Line 832... |
Line 839... |
|
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0)
|
if (resetn == 1'b0)
|
pc <= #1 16'h0;
|
pc <= 16'h0;
|
else if (pc_wr_r2)
|
else if (pc_wr_r2)
|
pc <= #1 pc_buf;
|
pc <= pc_buf;
|
else if (rd && !int_ack_t && !(pc_wr && (pc_wr_sel != `OC8051_PIS_AH)) && !pc_wr_r)
|
else if (rd && !int_ack_t && !(pc_wr && (pc_wr_sel != `OC8051_PIS_AH)) && !pc_wr_r)
|
pc <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
|
pc <= pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
|
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0)
|
if (resetn == 1'b0)
|
pc_next <= #1 16'h0;
|
pc_next <= 16'h0;
|
else if (pc_wr_r2)
|
else if (pc_wr_r2)
|
pc_next <= #1 pc_buf;
|
pc_next <= pc_buf;
|
else if (rd && !int_ack_t)
|
else if (rd && !int_ack_t)
|
pc_next <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
|
pc_next <= pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
|
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
pc_buf <= #1 `OC8051_RST_PC;
|
pc_buf <= `OC8051_RST_PC;
|
end else if (pc_wr) begin
|
end else if (pc_wr) begin
|
//
|
//
|
//case of writing new value to pc (jupms)
|
//case of writing new value to pc (jupms)
|
case (pc_wr_sel) /* synopsys full_case parallel_case */
|
case (pc_wr_sel) /* synopsys full_case parallel_case */
|
`OC8051_PIS_ALU: pc_buf <= #1 alu;
|
`OC8051_PIS_ALU: pc_buf <= alu;
|
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
|
`OC8051_PIS_AL: pc_buf[7:0] <= alu[7:0];
|
`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
|
`OC8051_PIS_AH: pc_buf[15:8] <= alu[7:0];
|
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
|
`OC8051_PIS_I11: pc_buf[10:0] <= {op1_out[7:5], op2_out};
|
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
|
`OC8051_PIS_I16: pc_buf <= {op2_out, op3_out};
|
`OC8051_PIS_SO1: pc_buf <= #1 pcs_result;
|
`OC8051_PIS_SO1: pc_buf <= pcs_result;
|
`OC8051_PIS_SO2: pc_buf <= #1 pcs_result;
|
`OC8051_PIS_SO2: pc_buf <= pcs_result;
|
|
default: pc_buf <= `OC8051_RST_PC;
|
endcase
|
endcase
|
// end else if (inc_pc) begin
|
// end else if (inc_pc) begin
|
end else begin
|
end else begin
|
//
|
//
|
//or just remember current
|
//or just remember current
|
pc_buf <= #1 pc_out;
|
pc_buf <= pc_out;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign pc_out = inc_pc ? pc_buf + 16'h4
|
assign pc_out = inc_pc ? pc_buf + 16'h4
|
| Line 883... |
Line 891... |
|
|
|
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0)
|
if (resetn == 1'b0)
|
ddat_ir <= #1 8'h00;
|
ddat_ir <= 8'h00;
|
else if (dack_i)
|
else if (dack_i)
|
ddat_ir <= #1 ddat_i;
|
ddat_ir <= ddat_i;
|
|
|
|
|
////////////////////////
|
////////////////////////
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
rn_r <= #1 5'd0;
|
rn_r <= 5'd0;
|
ri_r <= #1 8'h00;
|
ri_r <= 8'h00;
|
imm_r <= #1 8'h00;
|
imm_r <= 8'h00;
|
imm2_r <= #1 8'h00;
|
imm2_r <= 8'h00;
|
rd_addr_r <= #1 1'b0;
|
rd_addr_r <= 1'b0;
|
op1_r <= #1 8'h0;
|
op1_r <= 8'h0;
|
dack_ir <= #1 1'b0;
|
dack_ir <= 1'b0;
|
sp_r <= #1 1'b0;
|
sp_r <= 1'b0;
|
pc_wr_r <= #1 1'b0;
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pc_wr_r <= 1'b0;
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pc_wr_r2 <= #1 1'b0;
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pc_wr_r2 <= 1'b0;
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end else begin
|
end else begin
|
rn_r <= #1 rn;
|
rn_r <= rn;
|
ri_r <= #1 ri;
|
ri_r <= ri;
|
imm_r <= #1 imm;
|
imm_r <= imm;
|
imm2_r <= #1 imm2;
|
imm2_r <= imm2;
|
rd_addr_r <= #1 rd_addr[7];
|
rd_addr_r <= rd_addr[7];
|
op1_r <= #1 op1_out;
|
op1_r <= op1_out;
|
dack_ir <= #1 dack_i;
|
dack_ir <= dack_i;
|
sp_r <= #1 sp;
|
sp_r <= sp;
|
pc_wr_r <= #1 pc_wr && (pc_wr_sel != `OC8051_PIS_AH);
|
pc_wr_r <= pc_wr && (pc_wr_sel != `OC8051_PIS_AH);
|
pc_wr_r2 <= #1 pc_wr_r;
|
pc_wr_r2 <= pc_wr_r;
|
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
inc_pc_r <= #1 1'b1;
|
inc_pc_r <= 1'b1;
|
end else if (istb) begin
|
end else if (istb) begin
|
inc_pc_r <= #1 inc_pc;
|
inc_pc_r <= inc_pc;
|
end
|
end
|
|
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
|
|
initial
|
initial
|
