| Line 12... |
Line 12... |
//// nothing ////
|
//// nothing ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//////////////////////////////////////////////////////////////////////
|
|
//// v0.0 - Dinesh A, 17th Dec 2016
|
|
//// 1. External ROM Interface Removed
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
| Line 128... |
Line 130... |
op3_out,
|
op3_out,
|
|
|
//internal
|
//internal
|
idat_onchip,
|
idat_onchip,
|
|
|
//external
|
|
iack_i,
|
|
istb_o,
|
|
idat_i,
|
|
|
|
//external data ram
|
//external data ram
|
dadr_o,
|
dadr_o,
|
dwe_o,
|
dwe_o,
|
dstb_o,
|
dstb_o,
|
| Line 175... |
Line 173... |
input [2:0] mem_act;
|
input [2:0] mem_act;
|
input [7:0] in_ram,
|
input [7:0] in_ram,
|
sfr,
|
sfr,
|
acc,
|
acc,
|
sp_w;
|
sp_w;
|
input [31:0] idat_i;
|
|
|
|
output bit_out,
|
output bit_out,
|
mem_wait,
|
mem_wait,
|
reti;
|
reti;
|
output [7:0] iram_out,
|
output [7:0] iram_out,
|
| Line 201... |
Line 198... |
/////////////////////////////
|
/////////////////////////////
|
//
|
//
|
// rom_addr_sel
|
// rom_addr_sel
|
//
|
//
|
/////////////////////////////
|
/////////////////////////////
|
input iack_i;
|
|
input [7:0] des_acc,
|
input [7:0] des_acc,
|
des1,
|
des1,
|
des2;
|
des2;
|
output [15:0] iadr_o;
|
output [15:0] iadr_o;
|
|
|
| Line 267... |
Line 263... |
|
|
input [7:0] int_v;
|
input [7:0] int_v;
|
|
|
input [31:0] idat_onchip;
|
input [31:0] idat_onchip;
|
|
|
output int_ack,
|
output int_ack;
|
istb_o;
|
|
|
|
output [7:0] op1_out,
|
output [7:0] op1_out,
|
op3_out,
|
op3_out,
|
op2_out;
|
op2_out;
|
|
|
| Line 354... |
Line 349... |
assign alu = {des2, des_acc};
|
assign alu = {des2, des_acc};
|
assign ea_rom_sel = ea && ea_int;
|
assign ea_rom_sel = ea && ea_int;
|
assign wr_o = wr_i;
|
assign wr_o = wr_i;
|
assign wr_bit_o = wr_bit_i;
|
assign wr_bit_o = wr_bit_i;
|
|
|
//assign mem_wait = dmem_wait || imem_wait || pc_wr_r;
|
|
assign mem_wait = dmem_wait || imem_wait || pc_wr_r2;
|
assign mem_wait = dmem_wait || imem_wait || pc_wr_r2;
|
//assign mem_wait = dmem_wait || imem_wait;
|
|
assign istb_o = (istb || (istb_t & !iack_i)) && !dstb_o && !ea_rom_sel;
|
|
|
|
assign pc_wait = rd && (ea_rom_sel || (!istb_t && iack_i));
|
assign pc_wait = rd ;
|
|
|
assign wr_dat = des1;
|
assign wr_dat = des1;
|
|
|
|
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
| Line 398... |
Line 390... |
//
|
//
|
// ram_adr_sel
|
// ram_adr_sel
|
//
|
//
|
/////////////////////////////
|
/////////////////////////////
|
|
|
always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)
|
always @(*)
|
begin
|
begin
|
case (rd_sel) /* synopsys full_case parallel_case */
|
case (rd_sel) /* synopsys full_case parallel_case */
|
`OC8051_RRS_RN : rd_addr = {3'h0, rn};
|
`OC8051_RRS_RN : rd_addr = {3'h0, rn};
|
`OC8051_RRS_I : rd_addr = ri;
|
`OC8051_RRS_I : rd_addr = ri;
|
`OC8051_RRS_D : rd_addr = imm;
|
`OC8051_RRS_D : rd_addr = imm;
|
| Line 410... |
Line 402... |
|
|
`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
|
`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
|
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
|
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
|
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
|
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
|
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
|
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
|
// default : rd_addr = 2'bxx;
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
|
|
//
|
//
|
//
|
//
|
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
|
always @(*)
|
begin
|
begin
|
case (wr_sel) /* synopsys full_case parallel_case */
|
case (wr_sel) /* synopsys full_case parallel_case */
|
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
|
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
|
`OC8051_RWS_I : wr_addr = ri_r;
|
`OC8051_RWS_I : wr_addr = ri_r;
|
`OC8051_RWS_D : wr_addr = imm_r;
|
`OC8051_RWS_D : wr_addr = imm_r;
|
| Line 455... |
Line 446... |
/////////////////////////////
|
/////////////////////////////
|
//
|
//
|
// output address is alu destination
|
// output address is alu destination
|
// (instructions MOVC)
|
// (instructions MOVC)
|
|
|
//assign iadr_o = (istb_t & !iack_i) ? iadr_t : pc_out;
|
|
assign iadr_o = (istb_t) ? iadr_t : pc_out;
|
assign iadr_o = (istb_t) ? iadr_t : pc_out;
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
| Line 474... |
Line 464... |
imem_wait <= #1 1'b1;
|
imem_wait <= #1 1'b1;
|
end else if (ea_rom_sel && imem_wait) begin
|
end else if (ea_rom_sel && imem_wait) begin
|
imem_wait <= #1 1'b0;
|
imem_wait <= #1 1'b0;
|
end else if (!imem_wait && istb_t) begin
|
end else if (!imem_wait && istb_t) begin
|
istb_t <= #1 1'b0;
|
istb_t <= #1 1'b0;
|
end else if (iack_i) begin
|
|
imem_wait <= #1 1'b0;
|
|
idat_ir <= #1 idat_i [23:0];
|
|
end
|
end
|
end
|
end
|
|
|
/////////////////////////////
|
/////////////////////////////
|
//
|
//
|
| Line 547... |
Line 534... |
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
idat_cur <= #1 32'h0;
|
idat_cur <= #1 32'h0;
|
idat_old <= #1 32'h0;
|
idat_old <= #1 32'h0;
|
end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
|
end else if (inc_pc || pc_wr_r2) begin
|
idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i;
|
idat_cur <= #1 idat_onchip;
|
idat_old <= #1 idat_cur;
|
idat_old <= #1 idat_cur;
|
end
|
end
|
|
|
end
|
end
|
|
|
| Line 560... |
Line 547... |
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
cdata <= #1 8'h00;
|
cdata <= #1 8'h00;
|
cdone <= #1 1'b0;
|
cdone <= #1 1'b0;
|
end else if (istb_t) begin
|
end else if (istb_t) begin
|
cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0];
|
cdata <= #1 idat_onchip[7:0] ;
|
cdone <= #1 1'b1;
|
cdone <= #1 1'b1;
|
end else begin
|
end else begin
|
cdone <= #1 1'b0;
|
cdone <= #1 1'b0;
|
end
|
end
|
end
|
end
|
|
|
always @(op_pos or idat_cur or idat_old)
|
always @(*)
|
begin
|
begin
|
case (op_pos) /* synopsys parallel_case */
|
case (op_pos) /* synopsys parallel_case */
|
3'b000: begin
|
3'b000: begin
|
op1 = idat_old[7:0] ;
|
op1 = idat_old[7:0] ;
|
op2 = idat_old[15:8] ;
|
op2 = idat_old[15:8] ;
|
| Line 603... |
Line 590... |
op3 = idat_cur[31:24];
|
op3 = idat_cur[31:24];
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
/*assign op1 = ea_rom_sel ? idat_onchip[7:0] : op1_xt;
|
always @(*)
|
assign op2 = ea_rom_sel ? idat_onchip[15:8] : op2_xt;
|
|
assign op3 = ea_rom_sel ? idat_onchip[23:16] : op3_xt;*/
|
|
|
|
|
|
always @(dack_ir or ddat_ir or op1_o or iram_out or cdone or cdata)
|
|
if (dack_ir)
|
if (dack_ir)
|
op1_out = ddat_ir;
|
op1_out = ddat_ir;
|
else if (cdone)
|
else if (cdone)
|
op1_out = cdata;
|
op1_out = cdata;
|
else
|
else
|
op1_out = op1_o;
|
op1_out = op1_o;
|
|
|
assign op3_out = (rd) ? op3_o : op3_buff;
|
assign op3_out = (rd) ? op3_o : op3_buff;
|
assign op2_out = (rd) ? op2_o : op2_buff;
|
assign op2_out = (rd) ? op2_o : op2_buff;
|
|
|
always @(idat_i or iack_i or idat_ir or rd)
|
always @(*)
|
begin
|
begin
|
if (iack_i) begin
|
if (!rd) begin
|
op1_xt = idat_i[7:0];
|
|
op2_xt = idat_i[15:8];
|
|
op3_xt = idat_i[23:16];
|
|
end else if (!rd) begin
|
|
op1_xt = idat_ir[7:0];
|
op1_xt = idat_ir[7:0];
|
op2_xt = idat_ir[15:8];
|
op2_xt = idat_ir[15:8];
|
op3_xt = idat_ir[23:16];
|
op3_xt = idat_ir[23:16];
|
end else begin
|
end else begin
|
op1_xt = 8'h00;
|
op1_xt = 8'h00;
|
| Line 639... |
Line 617... |
end
|
end
|
|
|
|
|
//
|
//
|
// in case of interrupts
|
// in case of interrupts
|
always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)
|
always @(*)
|
begin
|
begin
|
if (int_ack_t && (iack_i || ea_rom_sel)) begin
|
if (int_ack_t) begin
|
op1_o = `OC8051_LCALL;
|
op1_o = `OC8051_LCALL;
|
op2_o = 8'h00;
|
op2_o = 8'h00;
|
op3_o = int_vec_buff;
|
op3_o = int_vec_buff;
|
end else begin
|
end else begin
|
op1_o = op1;
|
op1_o = op1;
|
| Line 678... |
Line 656... |
//
|
//
|
// pc
|
// pc
|
//
|
//
|
/////////////////////////////
|
/////////////////////////////
|
|
|
always @(op1_out)
|
always @(*)
|
begin
|
begin
|
casex (op1_out) /* synopsys parallel_case */
|
casex (op1_out) /* synopsys parallel_case */
|
`OC8051_ACALL : op_length = 2'h2;
|
`OC8051_ACALL : op_length = 2'h2;
|
`OC8051_AJMP : op_length = 2'h2;
|
`OC8051_AJMP : op_length = 2'h2;
|
|
|
| Line 753... |
Line 731... |
`OC8051_XRL_CD : op_length = 2'h3;
|
`OC8051_XRL_CD : op_length = 2'h3;
|
default: op_length = 2'h1;
|
default: op_length = 2'h1;
|
endcase
|
endcase
|
end
|
end
|
|
|
/*
|
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst) begin
|
|
op_length = 2'h2;
|
|
// end else if (pc_wait) begin
|
|
end else begin
|
|
casex (op1_out)
|
|
`OC8051_ACALL : op_length <= #1 2'h2;
|
|
`OC8051_AJMP : op_length <= #1 2'h2;
|
|
|
|
//op_code [7:3]
|
|
`OC8051_CJNE_R : op_length <= #1 2'h3;
|
|
`OC8051_DJNZ_R : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DR : op_length <= #1 2'h2;
|
|
`OC8051_MOV_CR : op_length <= #1 2'h2;
|
|
`OC8051_MOV_RD : op_length <= #1 2'h2;
|
|
|
|
//op_code [7:1]
|
|
`OC8051_CJNE_I : op_length <= #1 2'h3;
|
|
`OC8051_MOV_ID : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DI : op_length <= #1 2'h2;
|
|
`OC8051_MOV_CI : op_length <= #1 2'h2;
|
|
|
|
//op_code [7:0]
|
|
`OC8051_ADD_D : op_length <= #1 2'h2;
|
|
`OC8051_ADD_C : op_length <= #1 2'h2;
|
|
`OC8051_ADDC_D : op_length <= #1 2'h2;
|
|
`OC8051_ADDC_C : op_length <= #1 2'h2;
|
|
`OC8051_ANL_D : op_length <= #1 2'h2;
|
|
`OC8051_ANL_C : op_length <= #1 2'h2;
|
|
`OC8051_ANL_DD : op_length <= #1 2'h2;
|
|
`OC8051_ANL_DC : op_length <= #1 2'h3;
|
|
`OC8051_ANL_B : op_length <= #1 2'h2;
|
|
`OC8051_ANL_NB : op_length <= #1 2'h2;
|
|
`OC8051_CJNE_D : op_length <= #1 2'h3;
|
|
`OC8051_CJNE_C : op_length <= #1 2'h3;
|
|
`OC8051_CLR_B : op_length <= #1 2'h2;
|
|
`OC8051_CPL_B : op_length <= #1 2'h2;
|
|
`OC8051_DEC_D : op_length <= #1 2'h2;
|
|
`OC8051_DJNZ_D : op_length <= #1 2'h3;
|
|
`OC8051_INC_D : op_length <= #1 2'h2;
|
|
`OC8051_JB : op_length <= #1 2'h3;
|
|
`OC8051_JBC : op_length <= #1 2'h3;
|
|
`OC8051_JC : op_length <= #1 2'h2;
|
|
`OC8051_JNB : op_length <= #1 2'h3;
|
|
`OC8051_JNC : op_length <= #1 2'h2;
|
|
`OC8051_JNZ : op_length <= #1 2'h2;
|
|
`OC8051_JZ : op_length <= #1 2'h2;
|
|
`OC8051_LCALL : op_length <= #1 2'h3;
|
|
`OC8051_LJMP : op_length <= #1 2'h3;
|
|
`OC8051_MOV_D : op_length <= #1 2'h2;
|
|
`OC8051_MOV_C : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DA : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DD : op_length <= #1 2'h3;
|
|
`OC8051_MOV_CD : op_length <= #1 2'h3;
|
|
`OC8051_MOV_BC : op_length <= #1 2'h2;
|
|
`OC8051_MOV_CB : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DP : op_length <= #1 2'h3;
|
|
`OC8051_ORL_D : op_length <= #1 2'h2;
|
|
`OC8051_ORL_C : op_length <= #1 2'h2;
|
|
`OC8051_ORL_AD : op_length <= #1 2'h2;
|
|
`OC8051_ORL_CD : op_length <= #1 2'h3;
|
|
`OC8051_ORL_B : op_length <= #1 2'h2;
|
|
`OC8051_ORL_NB : op_length <= #1 2'h2;
|
|
`OC8051_POP : op_length <= #1 2'h2;
|
|
`OC8051_PUSH : op_length <= #1 2'h2;
|
|
`OC8051_SETB_B : op_length <= #1 2'h2;
|
|
`OC8051_SJMP : op_length <= #1 2'h2;
|
|
`OC8051_SUBB_D : op_length <= #1 2'h2;
|
|
`OC8051_SUBB_C : op_length <= #1 2'h2;
|
|
`OC8051_XCH_D : op_length <= #1 2'h2;
|
|
`OC8051_XRL_D : op_length <= #1 2'h2;
|
|
`OC8051_XRL_C : op_length <= #1 2'h2;
|
|
`OC8051_XRL_AD : op_length <= #1 2'h2;
|
|
`OC8051_XRL_CD : op_length <= #1 2'h3;
|
|
default: op_length <= #1 2'h1;
|
|
endcase
|
|
//
|
|
//in case of instructions that use more than one clock hold current pc
|
|
// end else begin
|
|
// pc= pc_buf;
|
|
end
|
|
end
|
|
*/
|
|
|
|
assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
|
assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
|
|
|
always @(posedge rst or posedge clk)
|
always @(posedge rst or posedge clk)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
op_pos <= #1 3'h0;
|
op_pos <= #1 3'h0;
|
end else if (pc_wr_r2) begin
|
end else if (pc_wr_r2) begin
|
op_pos <= #1 3'h4;// - op_length;////****??????????
|
op_pos <= #1 3'h4;
|
/* end else if (inc_pc & rd) begin
|
|
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
|
|
op_pos[1:0] <= #1 op_pos[1:0] + op_length;
|
|
// op_pos <= #1 {1'b0, op_pos[1:0]} + {1'b0, op_length};
|
|
end else if (rd) begin
|
|
op_pos <= #1 op_pos + {1'b0, op_length};
|
|
end*/
|
|
end else if (inc_pc & rd) begin
|
end else if (inc_pc & rd) begin
|
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
|
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
|
op_pos[1:0] <= #1 op_pos[1:0] + op_length;
|
op_pos[1:0] <= #1 op_pos[1:0] + op_length;
|
// op_pos <= #1 {1'b0, op_pos[1:0]} + {1'b0, op_length};
|
|
// end else if (istb & rd) begin
|
|
end else if (rd) begin
|
end else if (rd) begin
|
op_pos <= #1 op_pos + {1'b0, op_length};
|
op_pos <= #1 op_pos + {1'b0, op_length};
|
end
|
end
|
end
|
end
|
|
|
| Line 874... |
Line 758... |
int_ack_t <= #1 1'b0;
|
int_ack_t <= #1 1'b0;
|
int_vec_buff <= #1 8'h00;
|
int_vec_buff <= #1 8'h00;
|
end else if (intr) begin
|
end else if (intr) begin
|
int_ack_t <= #1 1'b1;
|
int_ack_t <= #1 1'b1;
|
int_vec_buff <= #1 int_v;
|
int_vec_buff <= #1 int_v;
|
end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0;
|
end else if (rd && !pc_wr_r2) int_ack_t <= #1 1'b0;
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) int_ack_buff <= #1 1'b0;
|
if (rst) int_ack_buff <= #1 1'b0;
|
else int_ack_buff <= #1 int_ack_t;
|
else int_ack_buff <= #1 int_ack_t;
|
|
|
| Line 920... |
Line 804... |
{pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
|
{pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
|
pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
|
pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
|
end else pcs_result = pc + {8'h00, pcs_source};
|
end else pcs_result = pc + {8'h00, pcs_source};
|
end
|
end
|
|
|
//assign pc = pc_buf - {13'h0, op_pos[2] | inc_pc_r, op_pos[1:0]}; ////******???
|
|
//assign pc = pc_buf - 16'h8 + {13'h0, op_pos}; ////******???
|
|
//assign pc = pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
pc <= #1 16'h0;
|
pc <= #1 16'h0;
|
else if (pc_wr_r2)
|
else if (pc_wr_r2)
|
| Line 973... |
Line 853... |
if (rst)
|
if (rst)
|
ddat_ir <= #1 8'h00;
|
ddat_ir <= #1 8'h00;
|
else if (dack_i)
|
else if (dack_i)
|
ddat_ir <= #1 ddat_i;
|
ddat_ir <= #1 ddat_i;
|
|
|
/*
|
|
|
|
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or ea_rom_sel or iack_i)
|
|
begin
|
|
if (int_buff || int_buff1) begin
|
|
//
|
|
//in case of interrupt hold valut, to be written to stack
|
|
pc= pc_buf;
|
|
// end else if (pis_l) begin
|
|
// pc = {pc_buf[22:8], alu[7:0]};
|
|
end else if (pc_wait) begin
|
|
casex (op1_out)
|
|
`OC8051_ACALL : pc= pc_buf + 16'h2;
|
|
`OC8051_AJMP : pc= pc_buf + 16'h2;
|
|
|
|
//op_code [7:3]
|
|
`OC8051_CJNE_R : pc= pc_buf + 16'h3;
|
|
`OC8051_DJNZ_R : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DR : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_CR : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_RD : pc= pc_buf + 16'h2;
|
|
|
|
//op_code [7:1]
|
|
`OC8051_CJNE_I : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_ID : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DI : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_CI : pc= pc_buf + 16'h2;
|
|
|
|
//op_code [7:0]
|
|
`OC8051_ADD_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ADD_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ADDC_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ADDC_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_DD : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_DC : pc= pc_buf + 16'h3;
|
|
`OC8051_ANL_B : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_NB : pc= pc_buf + 16'h2;
|
|
`OC8051_CJNE_D : pc= pc_buf + 16'h3;
|
|
`OC8051_CJNE_C : pc= pc_buf + 16'h3;
|
|
`OC8051_CLR_B : pc= pc_buf + 16'h2;
|
|
`OC8051_CPL_B : pc= pc_buf + 16'h2;
|
|
`OC8051_DEC_D : pc= pc_buf + 16'h2;
|
|
`OC8051_DJNZ_D : pc= pc_buf + 16'h3;
|
|
`OC8051_INC_D : pc= pc_buf + 16'h2;
|
|
`OC8051_JB : pc= pc_buf + 16'h3;
|
|
`OC8051_JBC : pc= pc_buf + 16'h3;
|
|
`OC8051_JC : pc= pc_buf + 16'h2;
|
|
`OC8051_JNB : pc= pc_buf + 16'h3;
|
|
`OC8051_JNC : pc= pc_buf + 16'h2;
|
|
`OC8051_JNZ : pc= pc_buf + 16'h2;
|
|
`OC8051_JZ : pc= pc_buf + 16'h2;
|
|
`OC8051_LCALL : pc= pc_buf + 16'h3;
|
|
`OC8051_LJMP : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_D : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_C : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DA : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DD : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_CD : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_BC : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_CB : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DP : pc= pc_buf + 16'h3;
|
|
`OC8051_ORL_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_AD : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_CD : pc= pc_buf + 16'h3;
|
|
`OC8051_ORL_B : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_NB : pc= pc_buf + 16'h2;
|
|
`OC8051_POP : pc= pc_buf + 16'h2;
|
|
`OC8051_PUSH : pc= pc_buf + 16'h2;
|
|
`OC8051_SETB_B : pc= pc_buf + 16'h2;
|
|
`OC8051_SJMP : pc= pc_buf + 16'h2;
|
|
`OC8051_SUBB_D : pc= pc_buf + 16'h2;
|
|
`OC8051_SUBB_C : pc= pc_buf + 16'h2;
|
|
`OC8051_XCH_D : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_D : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_C : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_AD : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_CD : pc= pc_buf + 16'h3;
|
|
default: pc= pc_buf + 16'h1;
|
|
endcase
|
|
//
|
|
//in case of instructions that use more than one clock hold current pc
|
|
end else begin
|
|
pc= pc_buf;
|
|
end
|
|
end
|
|
|
|
|
|
//
|
|
//interrupt buffer
|
|
always @(posedge clk or posedge rst)
|
|
if (rst) begin
|
|
int_buff1 <= #1 1'b0;
|
|
end else begin
|
|
int_buff1 <= #1 int_buff;
|
|
end
|
|
|
|
always @(posedge clk or posedge rst)
|
|
if (rst) begin
|
|
int_buff <= #1 1'b0;
|
|
end else if (intr) begin
|
|
int_buff <= #1 1'b1;
|
|
end else if (pc_wait)
|
|
int_buff <= #1 1'b0;
|
|
|
|
wire [7:0] pcs_source;
|
|
reg [15:0] pcs_result;
|
|
reg pcs_cy;
|
|
|
|
assign pcs_source = pc_wr_sel[0] ? op3_out : op2_out;
|
|
|
|
always @(pcs_source or pc or pcs_cy)
|
|
begin
|
|
if (pcs_source[7]) begin
|
|
{pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
|
|
pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
|
|
end else pcs_result = pc + {8'h00, pcs_source};
|
|
end
|
|
|
|
|
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst) begin
|
|
pc_buf <= #1 `OC8051_RST_PC;
|
|
end else begin
|
|
if (pc_wr) begin
|
|
//
|
|
//case of writing new value to pc (jupms)
|
|
case (pc_wr_sel)
|
|
`OC8051_PIS_ALU: pc_buf <= #1 alu;
|
|
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
|
|
`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
|
|
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
|
|
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
|
|
`OC8051_PIS_SO1: pc_buf <= #1 pcs_result;
|
|
`OC8051_PIS_SO2: pc_buf <= #1 pcs_result;
|
|
endcase
|
|
end else
|
|
//
|
|
//or just remember current
|
|
pc_buf <= #1 pc;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or posedge rst)
|
|
if (rst)
|
|
ddat_ir <= #1 8'h00;
|
|
else if (dack_i)
|
|
ddat_ir <= #1 ddat_i;
|
|
*/
|
|
|
|
////////////////////////
|
////////////////////////
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
rn_r <= #1 5'd0;
|
rn_r <= #1 5'd0;
|
ri_r <= #1 8'h00;
|
ri_r <= #1 8'h00;
|
