OpenCores
URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_memory_interface.v] - Diff between revs 18 and 20

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 18 Rev 20
Line 12... Line 12... 
////   nothing                                                    ////
 
////   nothing                                                    ////
 
////                                                              ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////  Author(s):                                                  ////
 
////      - Simon Teran, simont@opencores.org                     ////
 
////      - Simon Teran, simont@opencores.org                     ////
 
////      - Dinesh Annayya, dinesha@opencores.org                 ////
 
////      - Dinesh Annayya, dinesha@opencores.org                 ////
 
//////////////////////////////////////////////////////////////////////
 
////      - Dinesh Annayya, dinesha@opencores.org                 ////
 
////   v0.0 - Dinesh A, 17th Dec 2016
 
 
 
////        1. External ROM Interface Removed
 
 
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
////                                                              ////
Line 130... Line 128... 
     op3_out,
 
     op3_out,
 
 
 
 
 
//internal
 
//internal
 
     idat_onchip,
 
     idat_onchip,
 
 
 
 
 
 
 
//external
 
 
 
     iack_i,
 
 
 
     istb_o,
 
 
 
     idat_i,
 
 
 
 
 
//external data ram
 
//external data ram
 
     dadr_o,
 
     dadr_o,
 
     dwe_o,
 
     dwe_o,
 
     dstb_o,
 
     dstb_o,
Line 173... Line 175... 
input [2:0]   mem_act;
 
input [2:0]   mem_act;
 
input [7:0]   in_ram,
 
input [7:0]   in_ram,
 
              sfr,
 
              sfr,
 
              acc,
 
              acc,
 
              sp_w;
 
              sp_w;
 
 
 
input [31:0]  idat_i;
 
 
 
 
 
output        bit_out,
 
output        bit_out,
 
              mem_wait,
 
              mem_wait,
 
              reti;
 
              reti;
 
output [7:0]  iram_out,
 
output [7:0]  iram_out,
Line 198... Line 201... 
/////////////////////////////
 
/////////////////////////////
 
//
 
//
 
//  rom_addr_sel
 
//  rom_addr_sel
 
//
 
//
 
/////////////////////////////
 
/////////////////////////////
 
 
 
input         iack_i;
 
input [7:0]   des_acc,
 
input [7:0]   des_acc,
 
              des1,
 
              des1,
 
              des2;
 
              des2;
 
output [15:0] iadr_o;
 
output [15:0] iadr_o;
 
 
 
 
Line 263... Line 267... 
 
 
 
 
input  [7:0]  int_v;
 
input  [7:0]  int_v;
 
 
 
 
 
input  [31:0] idat_onchip;
 
input  [31:0] idat_onchip;
 
 
 
 
 
output        int_ack;
 
output        int_ack,
 
 
 
              istb_o;
 
 
 
 
 
output  [7:0] op1_out,
 
output  [7:0] op1_out,
 
              op3_out,
 
              op3_out,
 
              op2_out;
 
              op2_out;
 
 
 
 
Line 349... Line 354... 
assign alu        = {des2, des_acc};
 
assign alu        = {des2, des_acc};
 
assign ea_rom_sel = ea && ea_int;
 
assign ea_rom_sel = ea && ea_int;
 
assign wr_o       = wr_i;
 
assign wr_o       = wr_i;
 
assign wr_bit_o   = wr_bit_i;
 
assign wr_bit_o   = wr_bit_i;
 
 
 
 
 
 
 
//assign mem_wait   = dmem_wait || imem_wait || pc_wr_r;
 
assign mem_wait   = dmem_wait || imem_wait || pc_wr_r2;
 
assign mem_wait   = dmem_wait || imem_wait || pc_wr_r2;
 
 
 
//assign mem_wait   = dmem_wait || imem_wait;
 
 
 
assign istb_o     = (istb || (istb_t & !iack_i)) && !dstb_o && !ea_rom_sel;
 
 
 
 
 
assign pc_wait    = rd ;
 
assign pc_wait    = rd && (ea_rom_sel || (!istb_t && iack_i));
 
 
 
 
 
assign wr_dat     = des1;
 
assign wr_dat     = des1;
 
 
 
 
 
 
 
 
 
`ifdef OC8051_SIMULATION
 
`ifdef OC8051_SIMULATION
Line 390... Line 398... 
//
 
//
 
// ram_adr_sel
 
// ram_adr_sel
 
//
 
//
 
/////////////////////////////
 
/////////////////////////////
 
 
 
 
 
always @(*)
 
always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)
 
begin
 
begin
 
  case (rd_sel) /* synopsys full_case parallel_case */
 
  case (rd_sel) /* synopsys full_case parallel_case */
 
    `OC8051_RRS_RN   : rd_addr = {3'h0, rn};
 
    `OC8051_RRS_RN   : rd_addr = {3'h0, rn};
 
    `OC8051_RRS_I    : rd_addr = ri;
 
    `OC8051_RRS_I    : rd_addr = ri;
 
    `OC8051_RRS_D    : rd_addr = imm;
 
    `OC8051_RRS_D    : rd_addr = imm;
Line 402... Line 410... 
 
 
 
 
    `OC8051_RRS_B    : rd_addr = `OC8051_SFR_B;
 
    `OC8051_RRS_B    : rd_addr = `OC8051_SFR_B;
 
    `OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
 
    `OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
 
    `OC8051_RRS_PSW  : rd_addr = `OC8051_SFR_PSW;
 
    `OC8051_RRS_PSW  : rd_addr = `OC8051_SFR_PSW;
 
    `OC8051_RRS_ACC  : rd_addr = `OC8051_SFR_ACC;
 
    `OC8051_RRS_ACC  : rd_addr = `OC8051_SFR_ACC;
 
 
 
//    default          : rd_addr = 2'bxx;
 
  endcase
 
  endcase
 
 
 
 
 
end
 
end
 
 
 
 
 
 
 
 
 
//
 
//
 
//
 
//
 
always @(*)
 
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
 
begin
 
begin
 
  case (wr_sel) /* synopsys full_case parallel_case */
 
  case (wr_sel) /* synopsys full_case parallel_case */
 
    `OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
 
    `OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
 
    `OC8051_RWS_I  : wr_addr = ri_r;
 
    `OC8051_RWS_I  : wr_addr = ri_r;
 
    `OC8051_RWS_D  : wr_addr = imm_r;
 
    `OC8051_RWS_D  : wr_addr = imm_r;
Line 446... Line 455... 
/////////////////////////////
 
/////////////////////////////
 
//
 
//
 
// output address is alu destination
 
// output address is alu destination
 
// (instructions MOVC)
 
// (instructions MOVC)
 
 
 
 
 
 
 
//assign iadr_o = (istb_t & !iack_i) ? iadr_t : pc_out;
 
assign iadr_o = (istb_t) ? iadr_t : pc_out;
 
assign iadr_o = (istb_t) ? iadr_t : pc_out;
 
 
 
 
 
 
 
 
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or posedge rst)
 
begin
 
begin
Line 464... Line 474... 
    imem_wait <= #1 1'b1;
 
    imem_wait <= #1 1'b1;
 
  end else if (ea_rom_sel && imem_wait) begin
 
  end else if (ea_rom_sel && imem_wait) begin
 
    imem_wait <= #1 1'b0;
 
    imem_wait <= #1 1'b0;
 
  end else if (!imem_wait && istb_t) begin
 
  end else if (!imem_wait && istb_t) begin
 
    istb_t <= #1 1'b0;
 
    istb_t <= #1 1'b0;
 
 
 
  end else if (iack_i) begin
 
 
 
    imem_wait <= #1 1'b0;
 
 
 
    idat_ir <= #1 idat_i [23:0];
 
  end
 
  end
 
end
 
end
 
 
 
 
 
/////////////////////////////
 
/////////////////////////////
 
//
 
//
Line 534... Line 547... 
always @(posedge clk or posedge rst)
 
always @(posedge clk or posedge rst)
 
begin
 
begin
 
  if (rst) begin
 
  if (rst) begin
 
    idat_cur <= #1 32'h0;
 
    idat_cur <= #1 32'h0;
 
    idat_old <= #1 32'h0;
 
    idat_old <= #1 32'h0;
 
  end else if (inc_pc || pc_wr_r2) begin
 
  end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
 
    idat_cur <= #1 idat_onchip;
 
    idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i;
 
    idat_old <= #1 idat_cur;
 
    idat_old <= #1 idat_cur;
 
  end
 
  end
 
 
 
 
 
end
 
end
 
 
 
 
Line 547... Line 560... 
begin
 
begin
 
  if (rst) begin
 
  if (rst) begin
 
    cdata <= #1 8'h00;
 
    cdata <= #1 8'h00;
 
    cdone <= #1 1'b0;
 
    cdone <= #1 1'b0;
 
  end else if (istb_t) begin
 
  end else if (istb_t) begin
 
    cdata <= #1 idat_onchip[7:0] ;
 
    cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0];
 
    cdone <= #1 1'b1;
 
    cdone <= #1 1'b1;
 
  end else begin
 
  end else begin
 
    cdone <= #1 1'b0;
 
    cdone <= #1 1'b0;
 
  end
 
  end
 
end
 
end
 
 
 
 
 
always @(*)
 
always @(op_pos or idat_cur or idat_old)
 
begin
 
begin
 
  case (op_pos)  /* synopsys parallel_case */
 
  case (op_pos)  /* synopsys parallel_case */
 
    3'b000: begin
 
    3'b000: begin
 
       op1 = idat_old[7:0]  ;
 
       op1 = idat_old[7:0]  ;
 
       op2 = idat_old[15:8] ;
 
       op2 = idat_old[15:8] ;
Line 590... Line 603... 
       op3 = idat_cur[31:24];
 
       op3 = idat_cur[31:24];
 
      end
 
      end
 
  endcase
 
  endcase
 
end
 
end
 
 
 
 
 
always @(*)
 
 
 
 
 
always @(dack_ir or ddat_ir or op1_o or iram_out or cdone or cdata)
 
  if (dack_ir)
 
  if (dack_ir)
 
    op1_out = ddat_ir;
 
    op1_out = ddat_ir;
 
  else if (cdone)
 
  else if (cdone)
 
    op1_out = cdata;
 
    op1_out = cdata;
 
  else
 
  else
 
    op1_out = op1_o;
 
    op1_out = op1_o;
 
 
 
 
 
assign op3_out = (rd) ? op3_o : op3_buff;
 
assign op3_out = (rd) ? op3_o : op3_buff;
 
assign op2_out = (rd) ? op2_o : op2_buff;
 
assign op2_out = (rd) ? op2_o : op2_buff;
 
 
 
 
 
always @(*)
 
always @(idat_i or iack_i or idat_ir or rd)
 
begin
 
begin
 
  if (!rd) begin
 
  if (iack_i) begin
 
 
 
    op1_xt = idat_i[7:0];
 
 
 
    op2_xt = idat_i[15:8];
 
 
 
    op3_xt = idat_i[23:16];
 
 
 
  end else if (!rd) begin
 
    op1_xt = idat_ir[7:0];
 
    op1_xt = idat_ir[7:0];
 
    op2_xt = idat_ir[15:8];
 
    op2_xt = idat_ir[15:8];
 
    op3_xt = idat_ir[23:16];
 
    op3_xt = idat_ir[23:16];
 
  end else begin
 
  end else begin
 
    op1_xt = 8'h00;
 
    op1_xt = 8'h00;
Line 617... Line 635... 
end
 
end
 
 
 
 
 
 
 
 
 
//
 
//
 
// in case of interrupts
 
// in case of interrupts
 
always @(*)
 
always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)
 
begin
 
begin
 
  if (int_ack_t) begin
 
  if (int_ack_t && (iack_i || ea_rom_sel)) begin
 
    op1_o = `OC8051_LCALL;
 
    op1_o = `OC8051_LCALL;
 
    op2_o = 8'h00;
 
    op2_o = 8'h00;
 
    op3_o = int_vec_buff;
 
    op3_o = int_vec_buff;
 
  end else begin
 
  end else begin
 
    op1_o = op1;
 
    op1_o = op1;
Line 656... Line 674... 
//
 
//
 
//  pc
 
//  pc
 
//
 
//
 
/////////////////////////////
 
/////////////////////////////
 
 
 
 
 
always @(*)
 
always @(op1_out)
 
begin
 
begin
 
        casex (op1_out) /* synopsys parallel_case */
 
        casex (op1_out) /* synopsys parallel_case */
 
          `OC8051_ACALL :  op_length = 2'h2;
 
          `OC8051_ACALL :  op_length = 2'h2;
 
          `OC8051_AJMP :   op_length = 2'h2;
 
          `OC8051_AJMP :   op_length = 2'h2;
 
 
 
 
Line 739... Line 757... 
always @(posedge rst or posedge clk)
 
always @(posedge rst or posedge clk)
 
begin
 
begin
 
  if (rst) begin
 
  if (rst) begin
 
    op_pos <= #1 3'h0;
 
    op_pos <= #1 3'h0;
 
  end else if (pc_wr_r2) begin
 
  end else if (pc_wr_r2) begin
 
    op_pos <= #1 3'h4;
 
    op_pos <= #1 3'h4;// - op_length;////****??????????
 
  end else if (inc_pc & rd) begin
 
  end else if (inc_pc & rd) begin
 
    op_pos[2]   <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
 
    op_pos[2]   <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
 
    op_pos[1:0] <= #1 op_pos[1:0] + op_length;
 
    op_pos[1:0] <= #1 op_pos[1:0] + op_length;
 
  end else if (rd) begin
 
  end else if (rd) begin
 
    op_pos <= #1 op_pos + {1'b0, op_length};
 
    op_pos <= #1 op_pos + {1'b0, op_length};
Line 758... Line 776... 
   int_ack_t <= #1 1'b0;
 
   int_ack_t <= #1 1'b0;
 
   int_vec_buff <= #1 8'h00;
 
   int_vec_buff <= #1 8'h00;
 
 end else if (intr) begin
 
 end else if (intr) begin
 
   int_ack_t <= #1 1'b1;
 
   int_ack_t <= #1 1'b1;
 
   int_vec_buff <= #1 int_v;
 
   int_vec_buff <= #1 int_v;
 
 end else if (rd && !pc_wr_r2) int_ack_t <= #1 1'b0;
 
 end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0;
 
 
 
 
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or posedge rst)
 
  if (rst) int_ack_buff <= #1 1'b0;
 
  if (rst) int_ack_buff <= #1 1'b0;
 
  else int_ack_buff <= #1 int_ack_t;
 
  else int_ack_buff <= #1 int_ack_t;
 
 
 
 
Line 804... Line 822... 
    {pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
 
    {pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
 
    pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
 
    pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
 
  end else pcs_result = pc + {8'h00, pcs_source};
 
  end else pcs_result = pc + {8'h00, pcs_source};
 
end
 
end
 
 
 
 
 
 
 
 
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or posedge rst)
 
begin
 
begin
 
  if (rst)
 
  if (rst)
 
    pc <= #1 16'h0;
 
    pc <= #1 16'h0;
 
  else if (pc_wr_r2)
 
  else if (pc_wr_r2)
Line 853... Line 872... 
  if (rst)
 
  if (rst)
 
    ddat_ir <= #1 8'h00;
 
    ddat_ir <= #1 8'h00;
 
  else if (dack_i)
 
  else if (dack_i)
 
    ddat_ir <= #1 ddat_i;
 
    ddat_ir <= #1 ddat_i;
 
 
 
 
 
 
 
 
 
////////////////////////
 
////////////////////////
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or posedge rst)
 
  if (rst) begin
 
  if (rst) begin
 
    rn_r      <= #1 5'd0;
 
    rn_r      <= #1 5'd0;
 
    ri_r      <= #1 8'h00;
 
    ri_r      <= #1 8'h00;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.