| Line 16... |
Line 16... |
//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 6th Jan 2017
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//// 1. pc_next logic added
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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| Line 98... |
Line 100... |
rd_sel,
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rd_sel,
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wr_sel,
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wr_sel,
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pc_wr_sel,
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pc_wr_sel,
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pc_wr,
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pc_wr,
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pc,
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pc,
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pc_next,
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rd,
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rd,
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mem_wait,
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mem_wait,
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mem_act,
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mem_act,
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istb,
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istb,
|
|
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| Line 301... |
Line 304... |
|
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input [2:0] pc_wr_sel;
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input [2:0] pc_wr_sel;
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|
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input pc_wr;
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input pc_wr;
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output [15:0] pc;
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output [15:0] pc;
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output [15:0] pc_next;
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|
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reg [15:0] pc;
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reg [15:0] pc,pc_next;
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|
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//
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//
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//pc program counter register, save current value
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//pc program counter register, save current value
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reg [15:0] pc_buf;
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reg [15:0] pc_buf;
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wire [15:0] alu;
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wire [15:0] alu;
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| Line 831... |
Line 835... |
begin
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begin
|
if (resetn == 1'b0)
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if (resetn == 1'b0)
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pc <= #1 16'h0;
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pc <= #1 16'h0;
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else if (pc_wr_r2)
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else if (pc_wr_r2)
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pc <= #1 pc_buf;
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pc <= #1 pc_buf;
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else if (rd & !int_ack_t)
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else if (rd && !int_ack_t && !(pc_wr && (pc_wr_sel != `OC8051_PIS_AH)) && !pc_wr_r)
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pc <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
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pc <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
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end
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end
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|
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always @(posedge clk or negedge resetn)
|
|
begin
|
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if (resetn == 1'b0)
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pc_next <= #1 16'h0;
|
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else if (pc_wr_r2)
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pc_next <= #1 pc_buf;
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else if (rd && !int_ack_t)
|
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pc_next <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
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end
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|
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
|
begin
|
if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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pc_buf <= #1 `OC8051_RST_PC;
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pc_buf <= #1 `OC8051_RST_PC;
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