| Line 14... |
Line 14... |
//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, simont@opencores.org ////
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//// - Dinesh Annayya, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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| Line 62... |
Line 65... |
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`include "top_defines.v"
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`include "top_defines.v"
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|
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module oc8051_ports (clk,
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module oc8051_ports (clk,
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rst,
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resetn,
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bit_in,
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bit_in,
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data_in,
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data_in,
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wr,
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wr,
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wr_bit,
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wr_bit,
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wr_addr,
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wr_addr,
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| Line 97... |
Line 100... |
`endif
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`endif
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rmw);
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rmw);
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input clk, //clock
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input clk, //clock
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rst, //reset
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resetn, //reset
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wr, //write [oc8051_decoder.wr -r]
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wr, //write [oc8051_decoder.wr -r]
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wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]
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wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]
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bit_in, //bit input [oc8051_alu.desCy]
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bit_in, //bit input [oc8051_alu.desCy]
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rmw; //read modify write feature [oc8051_decoder.rmw]
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rmw; //read modify write feature [oc8051_decoder.rmw]
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input [7:0] wr_addr, //write address [oc8051_ram_wr_sel.out]
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input [7:0] wr_addr, //write address [oc8051_ram_wr_sel.out]
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Line 149... |
assign p3_data = rmw ? p3_out : p3_in;
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assign p3_data = rmw ? p3_out : p3_in;
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`endif
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`endif
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//
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//
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// case of writing to port
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// case of writing to port
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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p0_out <= #1 `OC8051_RST_P0;
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p0_out <= #1 `OC8051_RST_P0;
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`endif
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`endif
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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