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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_64x32_dual_bist.v] - Diff between revs 20 and 25

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Rev 20	Rev 25
Line 14...	Line 14...
`//// Author(s): ////`	`//// Author(s): ////`
`//// - Simon Teran, simont@opencores.org ////`	`//// - Simon Teran, simont@opencores.org ////`
`//// - Dinesh Annayya, dinesha@opencores.org ////`	`//// - Dinesh Annayya, dinesha@opencores.org ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
	`//// v0.0 - Dinesh A, 5th Jan 2017`
	`//// 1. Active edge of reset changed from High to Low`
	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`	`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
`//// ////`	`//// ////`
`//// This source file may be used and distributed without ////`	`//// This source file may be used and distributed without ////`
`//// restriction provided that this copyright statement is not ////`	`//// restriction provided that this copyright statement is not ////`
Line 54...	Line 57...
`//`	`//`
`// duble port ram`	`// duble port ram`
`//`	`//`
`module oc8051_ram_64x32_dual_bist (`	`module oc8051_ram_64x32_dual_bist (`
`clk,`	`clk,`
`rst,`	`resetn,`

`adr0,`	`adr0,`
`dat0_o,`	`dat0_o,`
`en0,`	`en0,`

Line 79...	Line 82...

`parameter ADR_WIDTH = 6;`	`parameter ADR_WIDTH = 6;`

`input clk,`	`input clk,`
`wr1,`	`wr1,`
`rst,`	`resetn,`
`en0,`	`en0,`
`en1;`	`en1;`
`input [7:0] dat1_i;`	`input [7:0] dat1_i;`
`input [ADR_WIDTH-1:0] adr0;`	`input [ADR_WIDTH-1:0] adr0;`
`input [ADR_WIDTH-1:0] adr1;`	`input [ADR_WIDTH-1:0] adr1;`
Line 105...	Line 108...

`ifdef OC8051_RAM_XILINX	`ifdef OC8051_RAM_XILINX
`xilinx_ram_dp u_ram_dp(`	`xilinx_ram_dp u_ram_dp(`
`// read port`	`// read port`
`.CLKA(clk),`	`.CLKA(clk),`
`.RSTA(rst),`	`.RSTA(resetn),`
`.ENA(en0),`	`.ENA(en0),`
`.ADDRA(adr0),`	`.ADDRA(adr0),`
`.DIA(32'h00),`	`.DIA(32'h00),`
`.WEA(1'b0),`	`.WEA(1'b0),`
`.DOA(dat0_o),`	`.DOA(dat0_o),`

`// write port`	`// write port`
`.CLKB(clk),`	`.CLKB(clk),`
`.RSTB(rst),`	`.RSTB(resetn),`
`.ENB(en1),`	`.ENB(en1),`
`.ADDRB(adr1),`	`.ADDRB(adr1),`
`.DIB(dat1_i),`	`.DIB(dat1_i),`
`.WEB(wr1),`	`.WEB(wr1),`
`.DOB(dat1_o)`	`.DOB(dat1_o)`
Line 136...	Line 139...

`ifdef OC8051_RAM_GENERIC	`ifdef OC8051_RAM_GENERIC

`generic_dpram #(ADR_WIDTH, 32) u_ram_dp(`	`generic_dpram #(ADR_WIDTH, 32) u_ram_dp(`
`.rclk ( clk ),`	`.rclk ( clk ),`
`.rrst ( rst ),`	`.resetn ( resetn ),`
`.rce ( en0 ),`	`.rce ( en0 ),`
`.oe ( 1'b1 ),`	`.oe ( 1'b1 ),`
`.raddr ( adr0 ),`	`.raddr ( adr0 ),`
`.do ( dat0_o ),`	`.do ( dat0_o ),`

`.wclk ( clk ),`	`.wclk ( clk ),`
`.wrst ( rst ),`	`.wresetn ( resetn ),`
`.wce ( en1 ),`	`.wce ( en1 ),`
`.we ( wr1 ),`	`.we ( wr1 ),`
`.waddr ( adr1 ),`	`.waddr ( adr1 ),`
`.di ( dat1_i )`	`.di ( dat1_i )`
`);`	`);`
Line 158...	Line 161...
`reg [31:0] dat0_o;`	`reg [31:0] dat0_o;`
`//`	`//`
`// buffer`	`// buffer`
`reg [31:0] buff [0:(1<<ADR_WIDTH) -1];`	`reg [31:0] buff [0:(1<<ADR_WIDTH) -1];`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`begin`	`begin`
`if (rst)`	`if (resetn == 1'b0)`
`dat1_o <= #1 32'h0;`	`dat1_o <= #1 32'h0;`
`else if (wr1) begin`	`else if (wr1) begin`
`buff[adr1] <= #1 dat1_i;`	`buff[adr1] <= #1 dat1_i;`
`dat1_o <= #1 dat1_i;`	`dat1_o <= #1 dat1_i;`
`end else`	`end else`
`dat1_o <= #1 buff[adr1];`	`dat1_o <= #1 buff[adr1];`
`end`	`end`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`begin`	`begin`
`if (rst)`	`if (resetn == 1'b0)`
`dat0_o <= #1 32'h0;`	`dat0_o <= #1 32'h0;`
`else if ((adr0==adr1) & wr1)`	`else if ((adr0==adr1) & wr1)`
`dat0_o <= #1 dat1_i;`	`dat0_o <= #1 dat1_i;`
`else`	`else`
`dat0_o <= #1 buff[adr0];`	`dat0_o <= #1 buff[adr0];`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_64x32_dual_bist.v] - Diff between revs 20 and 25