| Line 16... |
Line 16... |
//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 19th Jan 2017
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//// 1. Lint Warning fixes
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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| Line 536... |
Line 538... |
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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adr0_r <= #1 8'h00;
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adr0_r <= 8'h00;
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ram_wr_sel_r <= #1 3'b000;
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ram_wr_sel_r <= 3'b000;
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wr_bit_r <= #1 1'b0;
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wr_bit_r <= 1'b0;
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// wait_data <= #1 1'b0;
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// wait_data <= 1'b0;
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end else begin
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end else begin
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adr0_r <= #1 adr0;
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adr0_r <= adr0;
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ram_wr_sel_r <= #1 ram_wr_sel;
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ram_wr_sel_r <= ram_wr_sel;
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wr_bit_r <= #1 wr_bit;
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wr_bit_r <= wr_bit;
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end
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end
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assign comp_wait = !(
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assign comp_wait = !(
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((comp_sel==`OC8051_CSS_AZ) &
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((comp_sel==`OC8051_CSS_AZ) &
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((wr_sfr==`OC8051_WRS_ACC1) |
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((wr_sfr==`OC8051_WRS_ACC1) |
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| Line 567... |
Line 569... |
//
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//
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//set output in case of address (byte)
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//set output in case of address (byte)
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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dat0 <= #1 8'h00;
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dat0 <= 8'h00;
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wait_data <= #1 1'b0;
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wait_data <= 1'b0;
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end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
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end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
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dat0 <= #1 des_acc;
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dat0 <= des_acc;
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wait_data <= #1 1'b0;
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wait_data <= 1'b0;
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end else if (
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end else if (
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(
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(
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((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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// ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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// ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r) | //write and read same address
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r) | //write and read same address
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(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address
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(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address
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) & !wait_data) begin
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) & !wait_data) begin
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wait_data <= #1 1'b1;
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wait_data <= 1'b1;
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end else if ((
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end else if ((
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((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
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((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
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((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
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) & !wait_data) begin
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) & !wait_data) begin
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wait_data <= #1 1'b1;
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wait_data <= 1'b1;
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|
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end else begin
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end else begin
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case (adr0) /* synopsys full_case parallel_case */
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case (adr0) /* synopsys full_case parallel_case */
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`OC8051_SFR_ACC: dat0 <= #1 acc;
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`OC8051_SFR_ACC: dat0 <= acc;
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`OC8051_SFR_PSW: dat0 <= #1 psw;
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`OC8051_SFR_PSW: dat0 <= psw;
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|
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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`OC8051_SFR_P0: dat0 <= #1 p0_data;
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`OC8051_SFR_P0: dat0 <= p0_data;
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`endif
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`endif
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|
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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`OC8051_SFR_P1: dat0 <= #1 p1_data;
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`OC8051_SFR_P1: dat0 <= p1_data;
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`endif
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`endif
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|
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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`OC8051_SFR_P2: dat0 <= #1 p2_data;
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`OC8051_SFR_P2: dat0 <= p2_data;
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`endif
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`endif
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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`OC8051_SFR_P3: dat0 <= #1 p3_data;
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`OC8051_SFR_P3: dat0 <= p3_data;
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`endif
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`endif
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`endif
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`endif
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`OC8051_SFR_SP: dat0 <= #1 sp;
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`OC8051_SFR_SP: dat0 <= sp;
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`OC8051_SFR_B: dat0 <= #1 b_reg;
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`OC8051_SFR_B: dat0 <= b_reg;
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`OC8051_SFR_DPTR_HI: dat0 <= #1 dptr_hi;
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`OC8051_SFR_DPTR_HI: dat0 <= dptr_hi;
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`OC8051_SFR_DPTR_LO: dat0 <= #1 dptr_lo;
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`OC8051_SFR_DPTR_LO: dat0 <= dptr_lo;
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|
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`ifdef OC8051_UART
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`ifdef OC8051_UART
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`OC8051_SFR_SCON: dat0 <= #1 scon;
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`OC8051_SFR_SCON: dat0 <= scon;
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`OC8051_SFR_SBUF: dat0 <= #1 sbuf;
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`OC8051_SFR_SBUF: dat0 <= sbuf;
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`OC8051_SFR_PCON: dat0 <= #1 pcon;
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`OC8051_SFR_PCON: dat0 <= pcon;
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`endif
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`endif
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`ifdef OC8051_TC01
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`ifdef OC8051_TC01
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`OC8051_SFR_TH0: dat0 <= #1 th0;
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`OC8051_SFR_TH0: dat0 <= th0;
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`OC8051_SFR_TH1: dat0 <= #1 th1;
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`OC8051_SFR_TH1: dat0 <= th1;
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`OC8051_SFR_TL0: dat0 <= #1 tl0;
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`OC8051_SFR_TL0: dat0 <= tl0;
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`OC8051_SFR_TL1: dat0 <= #1 tl1;
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`OC8051_SFR_TL1: dat0 <= tl1;
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`OC8051_SFR_TMOD: dat0 <= #1 tmod;
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`OC8051_SFR_TMOD: dat0 <= tmod;
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`endif
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`endif
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`OC8051_SFR_IP: dat0 <= #1 ip;
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`OC8051_SFR_IP: dat0 <= ip;
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`OC8051_SFR_IE: dat0 <= #1 ie;
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`OC8051_SFR_IE: dat0 <= ie;
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`OC8051_SFR_TCON: dat0 <= #1 tcon;
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`OC8051_SFR_TCON: dat0 <= tcon;
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`ifdef OC8051_TC2
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`ifdef OC8051_TC2
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`OC8051_SFR_RCAP2H: dat0 <= #1 rcap2h;
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`OC8051_SFR_RCAP2H: dat0 <= rcap2h;
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`OC8051_SFR_RCAP2L: dat0 <= #1 rcap2l;
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`OC8051_SFR_RCAP2L: dat0 <= rcap2l;
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`OC8051_SFR_TH2: dat0 <= #1 th2;
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`OC8051_SFR_TH2: dat0 <= th2;
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`OC8051_SFR_TL2: dat0 <= #1 tl2;
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`OC8051_SFR_TL2: dat0 <= tl2;
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`OC8051_SFR_T2CON: dat0 <= #1 t2con;
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`OC8051_SFR_T2CON: dat0 <= t2con;
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`endif
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`endif
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// default: dat0 <= #1 8'h00;
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default: dat0 <= 8'h00;
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endcase
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endcase
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wait_data <= #1 1'b0;
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wait_data <= 1'b0;
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end
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end
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end
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end
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//
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//
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//set output in case of address (bit)
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//set output in case of address (bit)
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|
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
|
begin
|
if (resetn == 1'b0)
|
if (resetn == 1'b0)
|
bit_out <= #1 1'h0;
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bit_out <= 1'h0;
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else if (
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else if (
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((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
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((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
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((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
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((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
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)
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)
|
|
|
bit_out <= #1 dat1[adr0[2:0]];
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bit_out <= dat1[adr0[2:0]];
|
else if ((adr1==adr0) & we & wr_bit_r)
|
else if ((adr1==adr0) & we & wr_bit_r)
|
bit_out <= #1 bit_in;
|
bit_out <= bit_in;
|
else
|
else
|
case (adr0[7:3]) /* synopsys full_case parallel_case */
|
case (adr0[7:3]) /* synopsys full_case parallel_case */
|
`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
|
`OC8051_SFR_B_ACC: bit_out <= acc[adr0[2:0]];
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`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
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`OC8051_SFR_B_PSW: bit_out <= psw[adr0[2:0]];
|
|
|
`ifdef OC8051_PORTS
|
`ifdef OC8051_PORTS
|
`ifdef OC8051_PORT0
|
`ifdef OC8051_PORT0
|
`OC8051_SFR_B_P0: bit_out <= #1 p0_data[adr0[2:0]];
|
`OC8051_SFR_B_P0: bit_out <= p0_data[adr0[2:0]];
|
`endif
|
`endif
|
|
|
`ifdef OC8051_PORT1
|
`ifdef OC8051_PORT1
|
`OC8051_SFR_B_P1: bit_out <= #1 p1_data[adr0[2:0]];
|
`OC8051_SFR_B_P1: bit_out <= p1_data[adr0[2:0]];
|
`endif
|
`endif
|
|
|
`ifdef OC8051_PORT2
|
`ifdef OC8051_PORT2
|
`OC8051_SFR_B_P2: bit_out <= #1 p2_data[adr0[2:0]];
|
`OC8051_SFR_B_P2: bit_out <= p2_data[adr0[2:0]];
|
`endif
|
`endif
|
|
|
`ifdef OC8051_PORT3
|
`ifdef OC8051_PORT3
|
`OC8051_SFR_B_P3: bit_out <= #1 p3_data[adr0[2:0]];
|
`OC8051_SFR_B_P3: bit_out <= p3_data[adr0[2:0]];
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`OC8051_SFR_B_B: bit_out <= #1 b_reg[adr0[2:0]];
|
`OC8051_SFR_B_B: bit_out <= b_reg[adr0[2:0]];
|
`OC8051_SFR_B_IP: bit_out <= #1 ip[adr0[2:0]];
|
`OC8051_SFR_B_IP: bit_out <= ip[adr0[2:0]];
|
`OC8051_SFR_B_IE: bit_out <= #1 ie[adr0[2:0]];
|
`OC8051_SFR_B_IE: bit_out <= ie[adr0[2:0]];
|
`OC8051_SFR_B_TCON: bit_out <= #1 tcon[adr0[2:0]];
|
`OC8051_SFR_B_TCON: bit_out <= tcon[adr0[2:0]];
|
|
|
`ifdef OC8051_UART
|
`ifdef OC8051_UART
|
`OC8051_SFR_B_SCON: bit_out <= #1 scon[adr0[2:0]];
|
`OC8051_SFR_B_SCON: bit_out <= scon[adr0[2:0]];
|
`endif
|
`endif
|
|
|
`ifdef OC8051_TC2
|
`ifdef OC8051_TC2
|
`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
|
`OC8051_SFR_B_T2CON: bit_out <= t2con[adr0[2:0]];
|
`endif
|
`endif
|
|
|
// default: bit_out <= #1 1'b0;
|
default: bit_out <= 1'b0;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
prescaler <= #1 4'h0;
|
prescaler <= 4'h0;
|
pres_ow <= #1 1'b0;
|
pres_ow <= 1'b0;
|
end else if (prescaler==4'b1011) begin
|
end else if (prescaler==4'b1011) begin
|
prescaler <= #1 4'h0;
|
prescaler <= 4'h0;
|
pres_ow <= #1 1'b1;
|
pres_ow <= 1'b1;
|
end else begin
|
end else begin
|
prescaler <= #1 prescaler + 4'h1;
|
prescaler <= prescaler + 4'h1;
|
pres_ow <= #1 1'b0;
|
pres_ow <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
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No newline at end of file
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No newline at end of file
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