OpenCores

Rev 2	Rev 25
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`//// Author(s): ////`	`//// Author(s): ////`
`//// - Simon Teran, simont@opencores.org ////`	`//// - Simon Teran, simont@opencores.org ////`
`//// - Dinesh Annayya, dinesha@opencores.org ////`	`//// - Dinesh Annayya, dinesha@opencores.org ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
	`//// v0.0 - Dinesh A, 5th Jan 2017`
	`//// 1. Active edge of reset changed from High to Low`
	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`	`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
`//// ////`	`//// ////`
`//// This source file may be used and distributed without ////`	`//// This source file may be used and distributed without ////`
`//// restriction provided that this copyright statement is not ////`	`//// restriction provided that this copyright statement is not ////`
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`include "top_defines.v"	`include "top_defines.v"



`module oc8051_tc (clk, rst,`	`module oc8051_tc (clk, resetn,`
`data_in,`	`data_in,`
`wr_addr,`	`wr_addr,`
`wr, wr_bit,`	`wr, wr_bit,`
`ie0, ie1,`	`ie0, ie1,`
`tr0, tr1,`	`tr0, tr1,`
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`tmod, tl0, th0, tl1, th1);`	`tmod, tl0, th0, tl1, th1);`

`input [7:0] wr_addr,`	`input [7:0] wr_addr,`
`data_in;`	`data_in;`
`input clk,`	`input clk,`
`rst,`	`resetn,`
`wr,`	`wr,`
`wr_bit,`	`wr_bit,`
`ie0,`	`ie0,`
`ie1,`	`ie1,`
`tr0,`	`tr0,`
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`assign tf1= tf1_0 \| tf1_1;`	`assign tf1= tf1_0 \| tf1_1;`

`//`	`//`
`// read or write from one of the addresses in tmod`	`// read or write from one of the addresses in tmod`
`//`	`//`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`begin`	`begin`
`if (rst) begin`	`if (resetn == 1'b0) begin`
tmod <=#1 `OC8051_RST_TMOD;	tmod <=#1 `OC8051_RST_TMOD;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
`tmod <= #1 data_in;`	`tmod <= #1 data_in;`
`end`	`end`

`//`	`//`
`// TIMER COUNTER 0`	`// TIMER COUNTER 0`
`//`	`//`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`begin`	`begin`
`if (rst) begin`	`if (resetn == 1'b0) begin`
tl0 <=#1 `OC8051_RST_TL0;	tl0 <=#1 `OC8051_RST_TL0;
th0 <=#1 `OC8051_RST_TH0;	th0 <=#1 `OC8051_RST_TH0;
`tf0 <= #1 1'b0;`	`tf0 <= #1 1'b0;`
`tf1_0 <= #1 1'b0;`	`tf1_0 <= #1 1'b0;`
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
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`end`	`end`

`//`	`//`
`// TIMER COUNTER 1`	`// TIMER COUNTER 1`
`//`	`//`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`begin`	`begin`
`if (rst) begin`	`if (resetn == 1'b0) begin`
tl1 <=#1 `OC8051_RST_TL1;	tl1 <=#1 `OC8051_RST_TL1;
th1 <=#1 `OC8051_RST_TH1;	th1 <=#1 `OC8051_RST_TH1;
`tf1_1 <= #1 1'b0;`	`tf1_1 <= #1 1'b0;`
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
`tl1 <= #1 data_in;`	`tl1 <= #1 data_in;`
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`endcase`	`endcase`
`end`	`end`
`end`	`end`


`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`if (rst) begin`	`if (resetn == 1'b0) begin`
`t0_buff <= #1 1'b0;`	`t0_buff <= #1 1'b0;`
`t1_buff <= #1 1'b0;`	`t1_buff <= #1 1'b0;`
`end else begin`	`end else begin`
`t0_buff <= #1 t0;`	`t0_buff <= #1 t0;`
`t1_buff <= #1 t1;`	`t1_buff <= #1 t1;`

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////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Simon Teran, simont@opencores.org                     ////

////      - Simon Teran, simont@opencores.org                     ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////   v0.0 - Dinesh A, 5th Jan 2017

////        1. Active edge of reset changed from High to Low

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

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`include "top_defines.v"

`include "top_defines.v"

module oc8051_tc (clk, rst,

module oc8051_tc (clk, resetn,

            data_in,

            data_in,

            wr_addr,

            wr_addr,

            wr, wr_bit,

            wr, wr_bit,

            ie0, ie1,

            ie0, ie1,

            tr0, tr1,

            tr0, tr1,

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Line 82...

            tmod, tl0, th0, tl1, th1);

            tmod, tl0, th0, tl1, th1);

input [7:0]  wr_addr,

input [7:0]  wr_addr,

             data_in;

             data_in;

input        clk,

input        clk,

             rst,

             resetn,

wr,

wr,

             wr_bit,

             wr_bit,

             ie0,

             ie0,

             ie1,

             ie1,

             tr0,

             tr0,

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assign tf1= tf1_0 | tf1_1;

assign tf1= tf1_0 | tf1_1;

//

//

// read or write from one of the addresses in tmod

// read or write from one of the addresses in tmod

//

//

always @(posedge clk or posedge rst)

always @(posedge clk or negedge resetn)

begin

begin

 if (rst) begin

 if (resetn == 1'b0) begin

   tmod <=#1 `OC8051_RST_TMOD;

   tmod <=#1 `OC8051_RST_TMOD;

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))

    tmod <= #1 data_in;

    tmod <= #1 data_in;

end

end

//

//

// TIMER COUNTER 0

// TIMER COUNTER 0

//

//

always @(posedge clk or posedge rst)

always @(posedge clk or negedge resetn)

begin

begin

 if (rst) begin

 if (resetn == 1'b0) begin

   tl0 <=#1 `OC8051_RST_TL0;

   tl0 <=#1 `OC8051_RST_TL0;

   th0 <=#1 `OC8051_RST_TH0;

   th0 <=#1 `OC8051_RST_TH0;

   tf0 <= #1 1'b0;

   tf0 <= #1 1'b0;

   tf1_0 <= #1 1'b0;

   tf1_0 <= #1 1'b0;

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin

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end

end

//

//

// TIMER COUNTER 1

// TIMER COUNTER 1

//

//

always @(posedge clk or posedge rst)

always @(posedge clk or negedge resetn)

begin

begin

 if (rst) begin

 if (resetn == 1'b0) begin

   tl1 <=#1 `OC8051_RST_TL1;

   tl1 <=#1 `OC8051_RST_TL1;

   th1 <=#1 `OC8051_RST_TH1;

   th1 <=#1 `OC8051_RST_TH1;

   tf1_1 <= #1 1'b0;

   tf1_1 <= #1 1'b0;

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin

   tl1 <= #1 data_in;

   tl1 <= #1 data_in;

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    endcase

    endcase

end

end

end

end

always @(posedge clk or posedge rst)

always @(posedge clk or negedge resetn)

  if (rst) begin

  if (resetn == 1'b0) begin

    t0_buff <= #1 1'b0;

    t0_buff <= #1 1'b0;

    t1_buff <= #1 1'b0;

    t1_buff <= #1 1'b0;

  end else begin

  end else begin

    t0_buff <= #1 t0;

    t0_buff <= #1 t0;

    t1_buff <= #1 t1;

    t1_buff <= #1 t1;

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