| Line 115... |
Line 115... |
assign cprl2 = t2con[0];
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assign cprl2 = t2con[0];
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|
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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t2con <= #1 `OC8051_RST_T2CON;
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t2con <= `OC8051_RST_T2CON;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
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t2con <= #1 data_in;
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t2con <= data_in;
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
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t2con[wr_addr[2:0]] <= #1 bit_in;
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t2con[wr_addr[2:0]] <= bit_in;
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end else if (tf2_set) begin
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end else if (tf2_set) begin
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t2con[7] <= #1 1'b1;
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t2con[7] <= 1'b1;
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end else if (exen2 & neg_trans) begin
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end else if (exen2 & neg_trans) begin
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t2con[6] <= #1 1'b1;
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t2con[6] <= 1'b1;
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end
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end
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end
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end
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//
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//
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| Line 138... |
Line 138... |
begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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//
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//
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// reset
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// reset
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//
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//
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tl2 <= #1 `OC8051_RST_TL2;
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tl2 <= `OC8051_RST_TL2;
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th2 <= #1 `OC8051_RST_TH2;
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th2 <= `OC8051_RST_TH2;
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brate2 <= #1 1'b0;
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brate2 <= 1'b0;
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tf2_set <= #1 1'b0;
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tf2_set <= 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
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//
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//
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// write to timer 2 high
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// write to timer 2 high
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//
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//
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th2 <= #1 data_in;
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th2 <= data_in;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
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//
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//
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// write to timer 2 low
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// write to timer 2 low
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//
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//
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tl2 <= #1 data_in;
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tl2 <= data_in;
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end else if (!(rclk | tclk) & !cprl2 & exen2 & neg_trans) begin
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end else if (!(rclk | tclk) & !cprl2 & exen2 & neg_trans) begin
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//
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//
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// avto reload mode, exen2=1, 0-1 transition on t2ex pin
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// avto reload mode, exen2=1, 0-1 transition on t2ex pin
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//
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//
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th2 <= #1 rcap2h;
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th2 <= rcap2h;
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tl2 <= #1 rcap2l;
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tl2 <= rcap2l;
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tf2_set <= #1 1'b0;
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tf2_set <= 1'b0;
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end else if (run) begin
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end else if (run) begin
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if (rclk | tclk) begin
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if (rclk | tclk) begin
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//
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//
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// boud rate generator mode
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// boud rate generator mode
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//
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//
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if (&{th2, tl2}) begin
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if (&{th2, tl2}) begin
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th2 <= #1 rcap2h;
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th2 <= rcap2h;
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tl2 <= #1 rcap2l;
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tl2 <= rcap2l;
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brate2 <= #1 1'b1;
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brate2 <= 1'b1;
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end else begin
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end else begin
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{brate2, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
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{brate2, th2, tl2} <= {1'b0, th2, tl2} + 17'h1;
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end
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end
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tf2_set <= #1 1'b0;
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tf2_set <= 1'b0;
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end else if (cprl2) begin
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end else if (cprl2) begin
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//
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//
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// capture mode
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// capture mode
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//
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//
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{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
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{tf2_set, th2, tl2} <= {1'b0, th2, tl2} + 17'h1;
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end else begin
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end else begin
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//
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//
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// auto reload mode
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// auto reload mode
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//
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//
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if (&{th2, tl2}) begin
|
if (&{th2, tl2}) begin
|
th2 <= #1 rcap2h;
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th2 <= rcap2h;
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tl2 <= #1 rcap2l;
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tl2 <= rcap2l;
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tf2_set <= #1 1'b1;
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tf2_set <= 1'b1;
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end else begin
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end else begin
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{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
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{tf2_set, th2, tl2} <= {1'b0, th2, tl2} + 17'h1;
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end
|
end
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end
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end
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end else tf2_set <= #1 1'b0;
|
end else tf2_set <= 1'b0;
|
end
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end
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|
|
|
|
//
|
//
|
// rcap2l, rcap2h
|
// rcap2l, rcap2h
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
rcap2l <= #1 `OC8051_RST_RCAP2L;
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rcap2l <= `OC8051_RST_RCAP2L;
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rcap2h <= #1 `OC8051_RST_RCAP2H;
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rcap2h <= `OC8051_RST_RCAP2H;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
|
rcap2h <= #1 data_in;
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rcap2h <= data_in;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
|
rcap2l <= #1 data_in;
|
rcap2l <= data_in;
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end else if (!(rclk | tclk) & exen2 & cprl2 & neg_trans) begin
|
end else if (!(rclk | tclk) & exen2 & cprl2 & neg_trans) begin
|
rcap2l <= #1 tl2;
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rcap2l <= tl2;
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rcap2h <= #1 th2;
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rcap2h <= th2;
|
end
|
end
|
end
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end
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|
|
|
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//
|
//
|
//
|
//
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
neg_trans <= #1 1'b0;
|
neg_trans <= 1'b0;
|
t2ex_r <= #1 1'b0;
|
t2ex_r <= 1'b0;
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end else if (t2ex) begin
|
end else if (t2ex) begin
|
neg_trans <= #1 1'b0;
|
neg_trans <= 1'b0;
|
t2ex_r <= #1 1'b1;
|
t2ex_r <= 1'b1;
|
end else if (t2ex_r) begin
|
end else if (t2ex_r) begin
|
neg_trans <= #1 1'b1;
|
neg_trans <= 1'b1;
|
t2ex_r <= #1 1'b0;
|
t2ex_r <= 1'b0;
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end else begin
|
end else begin
|
neg_trans <= #1 1'b0;
|
neg_trans <= 1'b0;
|
t2ex_r <= #1 t2ex_r;
|
t2ex_r <= t2ex_r;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
//
|
//
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
tc2_event <= #1 1'b0;
|
tc2_event <= 1'b0;
|
t2_r <= #1 1'b0;
|
t2_r <= 1'b0;
|
end else if (t2) begin
|
end else if (t2) begin
|
tc2_event <= #1 1'b0;
|
tc2_event <= 1'b0;
|
t2_r <= #1 1'b1;
|
t2_r <= 1'b1;
|
end else if (!t2 & t2_r) begin
|
end else if (!t2 & t2_r) begin
|
tc2_event <= #1 1'b1;
|
tc2_event <= 1'b1;
|
t2_r <= #1 1'b0;
|
t2_r <= 1'b0;
|
end else begin
|
end else begin
|
tc2_event <= #1 1'b0;
|
tc2_event <= 1'b0;
|
end
|
end
|
end
|
end
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|
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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