URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Diff between revs 2 and 11

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Rev 2	Rev 11
Line 12...	Line 12...
`//// nothing ////`	`//// nothing ////`
`//// ////`	`//// ////`
`//// Author(s): ////`	`//// Author(s): ////`
`//// - Simon Teran, simont@opencores.org ////`	`//// - Simon Teran, simont@opencores.org ////`
`//// - Dinesh Annayya, dinesha@opencores.org ////`	`//// - Dinesh Annayya, dinesha@opencores.org ////`
	`//////////////////////////////////////////////////////////////////////`
	`// v0.0 - Dinesh A, 8th Dec 2016`
	`// 1. External ROM Interface Removed`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`	`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
`//// ////`	`//// ////`
Line 109...	Line 112...


`include "top_defines.v"	`include "top_defines.v"

`module oc8051_top (wb_rst_i, wb_clk_i,`	`module oc8051_top (wb_rst_i, wb_clk_i,`
`//interface to instruction rom`
`wbi_adr_o,`
`wbi_dat_i,`
`wbi_stb_o,`
`wbi_ack_i,`
`wbi_cyc_o,`
`wbi_err_i,`

`//interface to data ram`	`//interface to data ram`
`wbd_dat_i,`	`wbd_dat_i,`
`wbd_dat_o,`	`wbd_dat_o,`
`wbd_adr_o,`	`wbd_adr_o,`
Line 189...	Line 185...
`wb_clk_i, // clock input`	`wb_clk_i, // clock input`
`int0_i, // interrupt 0`	`int0_i, // interrupt 0`
`int1_i, // interrupt 1`	`int1_i, // interrupt 1`
`ea_in, // external access`	`ea_in, // external access`
`wbd_ack_i, // data acknowalge`	`wbd_ack_i, // data acknowalge`
`wbi_ack_i, // instruction acknowlage`	`wbd_err_i; // data error`
`wbd_err_i, // data error`
`wbi_err_i; // instruction error`

`input [7:0] wbd_dat_i; // ram data input`	`input [7:0] wbd_dat_i; // ram data input`
`input [31:0] wbi_dat_i; // rom data input`

`output wbd_we_o, // data write enable`	`output wbd_we_o, // data write enable`
`wbd_stb_o, // data strobe`	`wbd_stb_o, // data strobe`
`wbd_cyc_o, // data cycle`	`wbd_cyc_o; // data cycle`
`wbi_stb_o, // instruction strobe`
`wbi_cyc_o; // instruction cycle`

`output [7:0] wbd_dat_o; // data output`	`output [7:0] wbd_dat_o; // data output`

`output [15:0] wbd_adr_o, // data address`	`output [15:0] wbd_adr_o; // data address`
`wbi_adr_o; // instruction address`

`ifdef OC8051_PORTS	`ifdef OC8051_PORTS

`ifdef OC8051_PORT0	`ifdef OC8051_PORT0
`input [7:0] p0_i; // port 0 input`	`input [7:0] p0_i; // port 0 input`
Line 697...	Line 687...
`.dptr_lo (dptr_lo ),`	`.dptr_lo (dptr_lo ),`
`.wait_data (wait_data )`	`.wait_data (wait_data )`
`);`	`);`










`ifdef OC8051_BIST	`ifdef OC8051_BIST
`assign scanb_soi=scanb_si;`	`assign scanb_soi=scanb_si;`
`endif	`endif

`ifdef OC8051_WB

`oc8051_wb_iinterface oc8051_wb_iinterface(`	`// EXTERNAL ROM OPTION is removed`
`.rst (wb_rst_i ),`	`assign idat_i = 'h0 ;`
`.clk (wb_clk_i ),`	`assign iack_i = 'h0 ;`
`// cpu`
`.adr_i (iadr_o ),`
`.dat_o (idat_i ),`
`.stb_i (istb_o ),`
`.ack_o (iack_i ),`
`.cyc_i (icyc_o ),`
`// external rom`
`.dat_i (wbi_dat_i ),`
`.stb_o (wbi_stb_o ),`
`.adr_o (wbi_adr_o ),`
`.ack_i (wbi_ack_i ),`
`.cyc_o (wbi_cyc_o )`
`);`

`ifdef OC8051_SIMULATION

`initial`
`begin`
`#1`
`$display("\t * ");`
`$display("\t * External rom interface: WB interface");`
`$display("\t * ");`
`end`

`endif

`else

`assign wbi_adr_o = iadr_o ;`
`assign idat_i = wbi_dat_i ;`
`assign wbi_stb_o = 1'b1 ;`
`assign iack_i = wbi_ack_i ;`
`assign wbi_cyc_o = 1'b1 ;`

`ifdef OC8051_SIMULATION	`ifdef OC8051_SIMULATION

`initial`	`initial`
`begin`	`begin`
Line 761...	Line 709...
`end`	`end`

`endif	`endif


`endif



`// synopsys translate_off`	`// synopsys translate_off`
`// Debug Purpose only`	`// Debug Purpose only`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Diff between revs 2 and 11