URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Diff between revs 18 and 20

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Rev 18	Rev 20
Line 346...	Line 346...
`wire [15:0] iadr_o;`	`wire [15:0] iadr_o;`


`//`	`//`
`// decoder`	`// decoder`
`oc8051_decoder oc8051_decoder1(`	`oc8051_decoder u_decoder(`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.rst (wb_rst_i ),`
`.op_in (op1_n ),`	`.op_in (op1_n ),`
`.op1_c (op1_cur ),`	`.op1_c (op1_cur ),`
`.ram_rd_sel_o (ram_rd_sel ),`	`.ram_rd_sel_o (ram_rd_sel ),`
Line 380...	Line 380...


`wire [7:0] sub_result;`	`wire [7:0] sub_result;`
`//`	`//`
`//alu`	`//alu`
`oc8051_alu oc8051_alu1(`	`oc8051_alu u_alu(`
`.rst (wb_rst_i ),`	`.rst (wb_rst_i ),`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.op_code (alu_op ),`	`.op_code (alu_op ),`
`.src1 (src1 ),`	`.src1 (src1 ),`
`.src2 (src2 ),`	`.src2 (src2 ),`
Line 401...	Line 401...
`.bit_in(bit_out)`	`.bit_in(bit_out)`
`);`	`);`

`//`	`//`
`//data ram`	`//data ram`
`oc8051_ram_top oc8051_ram_top1(`	`oc8051_ram_top u_ram_top(`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.rst (wb_rst_i ),`
`.rd_addr (rd_addr ),`	`.rd_addr (rd_addr ),`
`.rd_data (ram_data ),`	`.rd_data (ram_data ),`
`.wr_addr (wr_addr ),`	`.wr_addr (wr_addr ),`
Line 425...	Line 425...
`endif	`endif
`);`	`);`

`//`	`//`

`oc8051_alu_src_sel oc8051_alu_src_sel1(`	`oc8051_alu_src_sel u_alu_src_sel(`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.rst (wb_rst_i ),`
`.rd (rd ),`	`.rd (rd ),`

`.sel1 (src_sel1 ),`	`.sel1 (src_sel1 ),`
Line 450...	Line 450...
`);`	`);`


`//`	`//`
`//`	`//`
`oc8051_comp oc8051_comp1(`	`oc8051_comp u_comp(`
`.sel (comp_sel ),`	`.sel (comp_sel ),`
`.eq (eq ),`	`.eq (eq ),`
`.b_in (bit_out ),`	`.b_in (bit_out ),`
`.cy (cy ),`	`.cy (cy ),`
`.acc (acc ),`	`.acc (acc ),`
Line 463...	Line 463...


`//`	`//`
`//program rom`	`//program rom`
`ifdef OC8051_ROM	`ifdef OC8051_ROM
`oc8051_rom oc8051_rom1(`	`oc8051_rom u_rom(`
`.rst (wb_rst_i ),`	`.rst (wb_rst_i ),`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.ea_int (ea_int ),`	`.ea_int (ea_int ),`
`.addr (iadr_o ),`	`.addr (iadr_o ),`
`.data_o (idat_onchip )`	`.data_o (idat_onchip )`
Line 489...	Line 489...

`endif	`endif

`//`	`//`
`//`	`//`
`oc8051_cy_select oc8051_cy_select1(`	`oc8051_cy_select u_cy_select(`
`.cy_sel (cy_sel ),`	`.cy_sel (cy_sel ),`
`.cy_in (cy ),`	`.cy_in (cy ),`
`.data_in (bit_out ),`	`.data_in (bit_out ),`
`.data_out (alu_cy )`	`.data_out (alu_cy )`
`);`	`);`
`//`	`//`
`//`	`//`
`oc8051_indi_addr oc8051_indi_addr1 (`	`oc8051_indi_addr u_indi_addr (`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.rst (wb_rst_i ),`
`.wr_addr (wr_addr ),`	`.wr_addr (wr_addr ),`
`.data_in (wr_dat ),`	`.data_in (wr_dat ),`
`.wr (wr_o ),`	`.wr (wr_o ),`
Line 513...	Line 513...



`//`	`//`
`//`	`//`
`oc8051_memory_interface oc8051_memory_interface1(`	`oc8051_memory_interface u_memory_interface(`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.rst (wb_rst_i ),`
`// internal ram`	`// internal ram`
`.wr_i (wr ),`	`.wr_i (wr ),`
`.wr_o (wr_o ),`	`.wr_o (wr_o ),`
Line 591...	Line 591...


`//`	`//`
`//`	`//`

`oc8051_sfr oc8051_sfr1(`	`oc8051_sfr u_sfr(`
`.rst (wb_rst_i ),`	`.rst (wb_rst_i ),`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.adr0 (rd_addr[7:0] ),`	`.adr0 (rd_addr[7:0] ),`
`.adr1 (wr_addr[7:0] ),`	`.adr1 (wr_addr[7:0] ),`
`.dat0 (sfr_out ),`	`.dat0 (sfr_out ),`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Diff between revs 18 and 20