| Line 16... |
Line 16... |
//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 19th Jan 2017
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//// 1. Lint Warning fixes
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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| Line 135... |
Line 137... |
assign ri = scon[0];
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assign ri = scon[0];
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0)
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if (resetn == 1'b0)
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scon <= #1 `OC8051_RST_SCON;
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scon <= `OC8051_RST_SCON;
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else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
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else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
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scon <= #1 data_in;
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scon <= data_in;
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else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
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else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
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scon[wr_addr[2:0]] <= #1 bit_in;
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scon[wr_addr[2:0]] <= bit_in;
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else if (tx_done)
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else if (tx_done)
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scon[1] <= #1 1'b1;
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scon[1] <= 1'b1;
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else if (!rx_done) begin
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else if (!rx_done) begin
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if (scon[7:6]==2'b00) begin
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if (scon[7:6]==2'b00) begin
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scon[0] <= #1 1'b1;
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scon[0] <= 1'b1;
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end else if ((sbuf_rxd_tmp[11]) | !(scon[5])) begin
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end else if ((sbuf_rxd_tmp[11]) | !(scon[5])) begin
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scon[0] <= #1 1'b1;
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scon[0] <= 1'b1;
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scon[2] <= #1 sbuf_rxd_tmp[11];
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scon[2] <= sbuf_rxd_tmp[11];
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end else
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end else
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scon[2] <= #1 sbuf_rxd_tmp[11];
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scon[2] <= sbuf_rxd_tmp[11];
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end
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end
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end
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end
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//
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//
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//power control register
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//power control register
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| Line 162... |
Line 164... |
assign smod = pcon[7];
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assign smod = pcon[7];
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0)
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if (resetn == 1'b0)
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begin
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begin
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pcon <= #1 `OC8051_RST_PCON;
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pcon <= `OC8051_RST_PCON;
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end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
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end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
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pcon <= #1 data_in;
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pcon <= data_in;
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end
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end
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//
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//
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//serial port buffer (transmit)
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//serial port buffer (transmit)
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| Line 178... |
Line 180... |
assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
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assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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txd <= #1 1'b1;
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txd <= 1'b1;
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tr_count <= #1 4'd0;
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tr_count <= 4'd0;
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trans <= #1 1'b0;
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trans <= 1'b0;
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sbuf_txd <= #1 11'h00;
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sbuf_txd <= 11'h00;
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tx_done <= #1 1'b0;
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tx_done <= 1'b0;
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//
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//
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// start transmiting
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// start transmiting
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//
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//
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end else if (wr_sbuf) begin
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end else if (wr_sbuf) begin
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case (scon[7:6]) /* synopsys parallel_case */
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case (scon[7:6]) /* synopsys parallel_case */
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2'b00: begin // mode 0
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2'b00: begin // mode 0
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sbuf_txd <= #1 {3'b001, data_in};
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sbuf_txd <= {3'b001, data_in};
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end
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end
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2'b01: begin // mode 1
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2'b01: begin // mode 1
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sbuf_txd <= #1 {2'b01, data_in, 1'b0};
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sbuf_txd <= {2'b01, data_in, 1'b0};
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end
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end
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default: begin // mode 2 and mode 3
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default: begin // mode 2 and mode 3
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sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0};
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sbuf_txd <= {1'b1, tb8, data_in, 1'b0};
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end
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end
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endcase
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endcase
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trans <= #1 1'b1;
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trans <= 1'b1;
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tr_count <= #1 4'd0;
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tr_count <= 4'd0;
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tx_done <= #1 1'b0;
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tx_done <= 1'b0;
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//
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//
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// transmiting
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// transmiting
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//
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//
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end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0
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end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0
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begin
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begin
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if (~|sbuf_txd[10:1]) begin
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if (~|sbuf_txd[10:1]) begin
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trans <= #1 1'b0;
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trans <= 1'b0;
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tx_done <= #1 1'b1;
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tx_done <= 1'b1;
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end else begin
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end else begin
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{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
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{sbuf_txd, txd} <= {1'b0, sbuf_txd};
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tx_done <= #1 1'b0;
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tx_done <= 1'b0;
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end
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end
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end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3
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end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3
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tr_count <= #1 tr_count + 4'd1;
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tr_count <= tr_count + 4'd1;
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if (~|tr_count) begin
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if (~|tr_count) begin
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if (~|sbuf_txd[10:0]) begin
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if (~|sbuf_txd[10:0]) begin
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trans <= #1 1'b0;
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trans <= 1'b0;
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tx_done <= #1 1'b1;
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tx_done <= 1'b1;
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txd <= #1 1'b1;
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txd <= 1'b1;
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end else begin
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end else begin
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{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
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{sbuf_txd, txd} <= {1'b0, sbuf_txd};
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tx_done <= #1 1'b0;
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tx_done <= 1'b0;
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end
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end
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end
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end
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end else if (!trans) begin
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end else if (!trans) begin
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txd <= #1 1'b1;
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txd <= 1'b1;
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tx_done <= #1 1'b0;
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tx_done <= 1'b0;
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end
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end
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end
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end
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//
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//
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//
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//
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| Line 248... |
Line 250... |
end
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end
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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smod_clk_tr <= #1 1'b0;
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smod_clk_tr <= 1'b0;
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shift_tr <= #1 1'b0;
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shift_tr <= 1'b0;
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end else if (sc_clk_tr) begin
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end else if (sc_clk_tr) begin
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if (smod) begin
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if (smod) begin
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shift_tr <= #1 1'b1;
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shift_tr <= 1'b1;
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end else begin
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end else begin
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shift_tr <= #1 smod_clk_tr;
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shift_tr <= smod_clk_tr;
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smod_clk_tr <= #1 !smod_clk_tr;
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smod_clk_tr <= !smod_clk_tr;
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end
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end
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end else begin
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end else begin
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shift_tr <= #1 1'b0;
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shift_tr <= 1'b0;
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end
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end
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end
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end
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//
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//
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//serial port buffer (receive)
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//serial port buffer (receive)
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//
|
//
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always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
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begin
|
begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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re_count <= #1 4'd0;
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re_count <= 4'd0;
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receive <= #1 1'b0;
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receive <= 1'b0;
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sbuf_rxd <= #1 8'h00;
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sbuf_rxd <= 8'h00;
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sbuf_rxd_tmp <= #1 12'd0;
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sbuf_rxd_tmp <= 12'd0;
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rx_done <= #1 1'b1;
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rx_done <= 1'b1;
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rxd_r <= #1 1'b1;
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rxd_r <= 1'b1;
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rx_sam <= #1 2'b00;
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rx_sam <= 2'b00;
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end else if (!rx_done) begin
|
end else if (!rx_done) begin
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receive <= #1 1'b0;
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receive <= 1'b0;
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rx_done <= #1 1'b1;
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rx_done <= 1'b1;
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sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
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sbuf_rxd <= sbuf_rxd_tmp[10:3];
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end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
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end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
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{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};
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{sbuf_rxd_tmp, rx_done} <= {rxd, sbuf_rxd_tmp};
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end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
|
end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
|
re_count <= #1 re_count + 4'd1;
|
re_count <= re_count + 4'd1;
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case (re_count) /* synopsys full_case parallel_case */
|
case (re_count) /* synopsys full_case parallel_case */
|
4'h7: rx_sam[0] <= #1 rxd;
|
4'h7: rx_sam[0] <= rxd;
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4'h8: rx_sam[1] <= #1 rxd;
|
4'h8: rx_sam[1] <= rxd;
|
4'h9: begin
|
4'h9: begin
|
{sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};
|
{sbuf_rxd_tmp, rx_done} <= {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};
|
end
|
end
|
|
default : rx_sam <= 2'b00;
|
endcase
|
endcase
|
//
|
//
|
//start receiving
|
//start receiving
|
//
|
//
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end else if (scon[7:6]==2'b00) begin //start mode 0
|
end else if (scon[7:6]==2'b00) begin //start mode 0
|
rx_done <= #1 1'b1;
|
rx_done <= 1'b1;
|
if (ren && !ri && !receive) begin
|
if (ren && !ri && !receive) begin
|
receive <= #1 1'b1;
|
receive <= 1'b1;
|
sbuf_rxd_tmp <= #1 10'h0ff;
|
sbuf_rxd_tmp <= 10'h0ff;
|
end
|
end
|
end else if (ren & shift_re) begin
|
end else if (ren & shift_re) begin
|
rxd_r <= #1 rxd;
|
rxd_r <= rxd;
|
rx_done <= #1 1'b1;
|
rx_done <= 1'b1;
|
re_count <= #1 4'h0;
|
re_count <= 4'h0;
|
receive <= #1 (rxd_r & !rxd);
|
receive <= (rxd_r & !rxd);
|
sbuf_rxd_tmp <= #1 10'h1ff;
|
sbuf_rxd_tmp <= 10'h1ff;
|
end else if (!ren) begin
|
end else if (!ren) begin
|
rxd_r <= #1 rxd;
|
rxd_r <= rxd;
|
end else
|
end else
|
rx_done <= #1 1'b1;
|
rx_done <= 1'b1;
|
end
|
end
|
|
|
//
|
//
|
//
|
//
|
reg sc_clk_re, smod_clk_re;
|
reg sc_clk_re, smod_clk_re;
|
| Line 329... |
Line 332... |
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
smod_clk_re <= #1 1'b0;
|
smod_clk_re <= 1'b0;
|
shift_re <= #1 1'b0;
|
shift_re <= 1'b0;
|
end else if (sc_clk_re) begin
|
end else if (sc_clk_re) begin
|
if (smod) begin
|
if (smod) begin
|
shift_re <= #1 1'b1;
|
shift_re <= 1'b1;
|
end else begin
|
end else begin
|
shift_re <= #1 smod_clk_re;
|
shift_re <= smod_clk_re;
|
smod_clk_re <= #1 !smod_clk_re;
|
smod_clk_re <= !smod_clk_re;
|
end
|
end
|
end else begin
|
end else begin
|
shift_re <= #1 1'b0;
|
shift_re <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
| Line 352... |
Line 355... |
//
|
//
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
t1_ow_buf <= #1 1'b0;
|
t1_ow_buf <= 1'b0;
|
end else begin
|
end else begin
|
t1_ow_buf <= #1 t1_ow;
|
t1_ow_buf <= t1_ow;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
