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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//
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//
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//
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//
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//
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//
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|
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module oc8051_wb_iinterface(rst, clk,
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module oc8051_wb_iinterface(resetn, clk,
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adr_i, dat_o, cyc_i, stb_i, ack_o,
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adr_i, dat_o, cyc_i, stb_i, ack_o,
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adr_o, dat_i, cyc_o, stb_o, ack_i
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adr_o, dat_i, cyc_o, stb_o, ack_i
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);
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);
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//
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//
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// rst (in) reset - pin
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// resetn (in) reset - pin
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// clk (in) clock - pini
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// clk (in) clock - pini
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input rst, clk;
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input resetn, clk;
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//
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//
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// interface to oc8051 cpu
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// interface to oc8051 cpu
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//
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//
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// adr_i (in) address
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// adr_i (in) address
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assign dat_o = dat_i;
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assign dat_o = dat_i;
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//assign stb_o = stb_i || ack_i;
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//assign stb_o = stb_i || ack_i;
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assign cyc_o = stb_o;
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assign cyc_o = stb_o;
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//assign adr_o = ack_i ? adr : adr_i;
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//assign adr_o = ack_i ? adr : adr_i;
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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adr_o <= #1 16'h0000;
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adr_o <= #1 16'h0000;
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end else if (ack_i) begin
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end else if (ack_i) begin
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stb_o <= #1 stb_i;
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stb_o <= #1 stb_i;
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adr_o <= #1 adr_i;
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adr_o <= #1 adr_i;
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