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Line 15... |
//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Nov 26, 2016 ////
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//// Revision : Nov 26, 2016 ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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| Line 49... |
Line 52... |
fastsim_mode ,
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fastsim_mode ,
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mastermode ,
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mastermode ,
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xtal_clk ,
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xtal_clk ,
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clkout ,
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clkout ,
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gen_resetn ,
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gen_resetn ,
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risc_reset ,
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risc_resetn ,
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app_clk ,
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app_clk ,
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uart_ref_clk
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uart_ref_clk
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);
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);
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| Line 62... |
Line 65... |
input fastsim_mode ; // fast sim mode = 1
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input fastsim_mode ; // fast sim mode = 1
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input mastermode ; // 1 : Risc master mode
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input mastermode ; // 1 : Risc master mode
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input xtal_clk ; // Xtal clock-25Mhx
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input xtal_clk ; // Xtal clock-25Mhx
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output clkout ; // clock output, 250Mhz
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output clkout ; // clock output, 250Mhz
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output gen_resetn ; // internally generated reset
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output gen_resetn ; // internally generated reset
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output risc_reset ; // internally generated reset
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output risc_resetn ; // internally generated reset
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output app_clk ; // application clock
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output app_clk ; // application clock
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output uart_ref_clk ; // uart 16x Ref clock
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output uart_ref_clk ; // uart 16x Ref clock
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wire hard_reset_st ;
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wire hard_reset_st ;
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| Line 76... |
Line 79... |
wire slave_run_st ;
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wire slave_run_st ;
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reg pll_done ;
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reg pll_done ;
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reg [11:0] pll_count ;
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reg [11:0] pll_count ;
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reg [2:0] clkgen_ps ;
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reg [2:0] clkgen_ps ;
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reg gen_resetn ; // internally generated reset
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reg gen_resetn ; // internally generated reset
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reg risc_reset ; // internally generated reset
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reg risc_resetn ; // internally generated reset
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assign clkout = app_clk;
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assign clkout = app_clk;
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wire pllout;
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wire pllout;
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/***********************************************
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/***********************************************
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| Line 139... |
Line 142... |
************************************************/
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************************************************/
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always @(posedge xtal_clk or negedge reset_n )
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always @(posedge xtal_clk or negedge reset_n )
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begin
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begin
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if (!reset_n) begin
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if (!reset_n) begin
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gen_resetn <= 0;
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gen_resetn <= 0;
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risc_reset <= 1;
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risc_resetn <= 0;
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end else if(run_st ) begin
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end else if(run_st ) begin
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gen_resetn <= 1;
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gen_resetn <= 1;
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risc_reset <= 0;
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risc_resetn <= 1;
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end else if(slave_run_st ) begin
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end else if(slave_run_st ) begin
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gen_resetn <= 1;
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gen_resetn <= 1;
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risc_reset <= 1; // Keet Risc in Reset
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risc_resetn <= 0; // Keet Risc in Reset
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end else begin
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end else begin
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gen_resetn <= 0;
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gen_resetn <= 0;
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risc_reset <= 1;
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risc_resetn <= 0;
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end
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end
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end
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end
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/****************************************
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/****************************************
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