| Line 15... |
Line 15... |
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// ////
|
//// ////
|
//// Revision : Nov 26, 2016 ////
|
//// Revision : Nov 26, 2016 ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// v0 - Dinesh A, 26th Nov 2016
|
// v0.0 - Dinesh A, 26th Nov 2016
|
// 1. MAC related logic are remved
|
// 1. MAC related logic are remved
|
|
// v0.1 - Dinesh A, 1st Dec 2016
|
|
// 1. RAM and ROM are internally connected to interconnect
|
|
// 2. Memory Map Change
|
|
// 3. Remove the External ROM Option & Enabled Internal ROM
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
| Line 55... |
Line 59... |
fastsim_mode ,
|
fastsim_mode ,
|
mastermode ,
|
mastermode ,
|
xtal_clk ,
|
xtal_clk ,
|
clkout ,
|
clkout ,
|
reset_out_n ,
|
reset_out_n ,
|
|
ea_in ,
|
|
|
// Reg Bus Interface Signal
|
// Reg Bus Interface Signal
|
ext_reg_cs ,
|
ext_reg_cs ,
|
ext_reg_tid ,
|
ext_reg_tid ,
|
ext_reg_wr ,
|
ext_reg_wr ,
|
| Line 78... |
Line 83... |
|
|
|
|
spi_sck ,
|
spi_sck ,
|
spi_so ,
|
spi_so ,
|
spi_si ,
|
spi_si ,
|
spi_cs_n ,
|
spi_cs_n
|
|
|
|
|
// External ROM interface
|
|
wb_xrom_adr ,
|
|
wb_xrom_ack ,
|
|
wb_xrom_err ,
|
|
wb_xrom_wr ,
|
|
wb_xrom_rdata ,
|
|
wb_xrom_wdata ,
|
|
|
|
wb_xrom_stb ,
|
|
wb_xrom_cyc ,
|
|
|
|
// External RAM interface
|
|
wb_xram_adr ,
|
|
wb_xram_ack ,
|
|
wb_xram_err ,
|
|
wb_xram_wr ,
|
|
wb_xram_be ,
|
|
wb_xram_rdata ,
|
|
wb_xram_wdata ,
|
|
|
|
wb_xram_stb ,
|
|
wb_xram_cyc,
|
|
|
|
ea_in
|
|
|
|
|
|
|
|
);
|
);
|
|
|
| Line 119... |
Line 100... |
input reset_n ; // Active Low Reset
|
input reset_n ; // Active Low Reset
|
input scan_mode ; // scan mode
|
input scan_mode ; // scan mode
|
input scan_enable ; // scan enable
|
input scan_enable ; // scan enable
|
input fastsim_mode ; // Fast Sim Mode
|
input fastsim_mode ; // Fast Sim Mode
|
input mastermode ; // 1 : Risc master mode
|
input mastermode ; // 1 : Risc master mode
|
|
input ea_in ; // input for external access (ea signal)
|
|
// ea=0 program is in external rom
|
|
// ea=1 program is in internal rom
|
|
|
input xtal_clk ; // xtal clock 25Mhz
|
input xtal_clk ; // xtal clock 25Mhz
|
output clkout ; // clock output
|
output clkout ; // clock output
|
output reset_out_n ; // clock output
|
output reset_out_n ; // clock output
|
|
|
| Line 155... |
Line 139... |
output spi_sck ; // clock
|
output spi_sck ; // clock
|
output spi_so ; // data out
|
output spi_so ; // data out
|
input spi_si ; // data in
|
input spi_si ; // data in
|
output [3:0] spi_cs_n ; // chip select
|
output [3:0] spi_cs_n ; // chip select
|
|
|
//----------------------------------------
|
|
// 8051 core ROM related signals
|
|
//---------------------------------------
|
|
output [15:0] wb_xrom_adr ; // instruction address
|
|
input wb_xrom_ack ; // instruction acknowlage
|
|
output wb_xrom_err ; // instruction error
|
|
output wb_xrom_wr ; // instruction error
|
|
input [31:0] wb_xrom_rdata ; // rom data input
|
|
output [31:0] wb_xrom_wdata ; // rom data input
|
|
|
|
output wb_xrom_stb ; // instruction strobe
|
|
output wb_xrom_cyc ; // instruction cycle
|
|
|
|
|
|
//----------------------------------------
|
//----------------------------------------
|
// 8051 core RAM related signals
|
// 8051 core RAM related signals
|
//---------------------------------------
|
//---------------------------------------
|
output [15:0] wb_xram_adr ; // data-ram address
|
wire [15:0] wb_xram_adr ; // data-ram address
|
input wb_xram_ack ; // data-ram acknowlage
|
wire wb_xram_ack ; // data-ram acknowlage
|
output wb_xram_err ; // data-ram error
|
wire wb_xram_err ; // data-ram error
|
output wb_xram_wr ; // data-ram error
|
wire wb_xram_wr ; // data-ram error
|
output [3:0] wb_xram_be ; // Byte enable
|
wire [3:0] wb_xram_be ; // Byte enable
|
input [31:0] wb_xram_rdata ; // ram data input
|
wire [31:0] wb_xram_rdata ; // ram data input
|
output [31:0] wb_xram_wdata ; // ram data input
|
wire [31:0] wb_xram_wdata ; // ram data input
|
|
|
output wb_xram_stb ; // data-ram strobe
|
wire wb_xram_stb ; // data-ram strobe
|
output wb_xram_cyc ; // data-ram cycle
|
wire wb_xram_cyc ; // data-ram cycle
|
|
|
|
|
input ea_in ; // input for external access (ea signal)
|
|
// ea=0 program is in external rom
|
|
// ea=1 program is in internal rom
|
|
//---------------------------------------------
|
//---------------------------------------------
|
// 8051 Instruction ROM interface
|
// 8051 Instruction ROM interface
|
//---------------------------------------------
|
//---------------------------------------------
|
wire [15:0] wbi_risc_adr;
|
wire [15:0] wbi_risc_adr;
|
wire [31:0] wbi_risc_rdata;
|
wire [31:0] wbi_risc_rdata;
|
| Line 221... |
Line 189... |
wire [3:0] reg_spi_be ;
|
wire [3:0] reg_spi_be ;
|
wire [31:0] reg_spi_rdata ;
|
wire [31:0] reg_spi_rdata ;
|
wire reg_spi_ack ;
|
wire reg_spi_ack ;
|
|
|
wire [3:0] wb_xrom_be ;
|
wire [3:0] wb_xrom_be ;
|
wire [3:0] wb_xram_be ;
|
|
|
|
wire [7:0] p0 ;
|
wire [7:0] p0 ;
|
wire [7:0] p1 ;
|
wire [7:0] p1 ;
|
wire [7:0] p2 ;
|
wire [7:0] p2 ;
|
wire [7:0] p3 ;
|
wire [7:0] p3 ;
|
| Line 240... |
Line 207... |
assign reset_out_n = gen_resetn;
|
assign reset_out_n = gen_resetn;
|
|
|
|
|
assign wb_xram_adr[15] = 0;
|
assign wb_xram_adr[15] = 0;
|
assign wb_xram_adr[1:0] = 2'b00;
|
assign wb_xram_adr[1:0] = 2'b00;
|
assign wb_xrom_adr[15:13] = 0;
|
|
|
|
wire [9:0] cfg_tx_buf_qbase_addr;
|
|
wire [9:0] cfg_rx_buf_qbase_addr;
|
|
|
|
|
|
assign reg_uart_addr[1:0] = 2'b0;
|
assign reg_uart_addr[1:0] = 2'b0;
|
assign reg_spi_addr[1:0] = 2'b0;
|
assign reg_spi_addr[1:0] = 2'b0;
|
//-------------------------------------------
|
//-------------------------------------------
|
// clock-gen instantiation
|
// clock-gen instantiation
|
| Line 282... |
Line 244... |
//------------------------------
|
//------------------------------
|
// 8051 Data Memory Map
|
// 8051 Data Memory Map
|
// 0x0000 to 0x7FFFF - Data Memory
|
// 0x0000 to 0x7FFFF - Data Memory
|
// 0x8000 to 0x8FFF - SPI
|
// 0x8000 to 0x8FFF - SPI
|
// 0x9000 to 0x9FFF - UART
|
// 0x9000 to 0x9FFF - UART
|
// 0xA000 to 0xAFFF - MAC Core
|
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
// Target ID Mapping
|
// Target ID Mapping
|
// 4'b0100 -- MAC core
|
// 4'b0010 -- UART
|
// 4'b0011 -- UART
|
// 4'b0001 -- SPI core
|
// 4'b0010 -- SPI core
|
// 4'b0000 -- External RAM
|
// 4'b0001 -- External RAM
|
|
// 4'b0000 -- External ROM
|
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
//
|
//
|
wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0001 :
|
wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :
|
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 :
|
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
|
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100;
|
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
|
|
|
wb_crossbar #(.WB_MASTER(3),
|
wb_crossbar #(.WB_MASTER(3),
|
.WB_SLAVE(4),
|
.WB_SLAVE(3),
|
.D_WD(32),
|
.D_WD(32),
|
.BE_WD(4),
|
.BE_WD(4),
|
.ADR_WD(13),
|
.ADR_WD(13),
|
.TAR_WD(4))
|
.TAR_WD(4))
|
u_wb_crossbar (
|
u_wb_crossbar (
|
| Line 340... |
Line 299... |
|
|
.wbd_ack_master ({wbi_risc_ack,
|
.wbd_ack_master ({wbi_risc_ack,
|
wbd_risc_ack,
|
wbd_risc_ack,
|
ext_reg_ack } ),
|
ext_reg_ack } ),
|
|
|
.wbd_stb_master ({wbi_risc_stb,
|
.wbd_stb_master ({1'b0,
|
wbd_risc_stb,
|
wbd_risc_stb,
|
ext_reg_cs} ),
|
ext_reg_cs} ),
|
|
|
.wbd_cyc_master ({wbi_risc_stb|wbi_risc_ack,
|
.wbd_cyc_master ({1'b0,
|
wbd_risc_stb|wbd_risc_ack,
|
wbd_risc_stb|wbd_risc_ack,
|
ext_reg_cs|ext_reg_ack }),
|
ext_reg_cs|ext_reg_ack }),
|
|
|
.wbd_err_master (),
|
.wbd_err_master (),
|
.wbd_rty_master (),
|
.wbd_rty_master (),
|
|
|
// Slave Interface Signal
|
// Slave Interface Signal
|
.wbd_din_slave ({reg_uart_wdata,
|
.wbd_din_slave ({reg_uart_wdata,
|
reg_spi_wdata,
|
reg_spi_wdata,
|
wb_xram_wdata,
|
wb_xram_wdata
|
wb_xrom_wdata
|
|
}),
|
}),
|
|
|
.wbd_dout_slave ({reg_uart_rdata,
|
.wbd_dout_slave ({reg_uart_rdata,
|
reg_spi_rdata,
|
reg_spi_rdata,
|
{wb_xram_rdata},
|
{wb_xram_rdata}
|
wb_xrom_rdata
|
|
}),
|
}),
|
|
|
.wbd_adr_slave ({reg_uart_addr[14:2],
|
.wbd_adr_slave ({reg_uart_addr[14:2],
|
reg_spi_addr[14:2],
|
reg_spi_addr[14:2],
|
wb_xram_adr[14:2],
|
wb_xram_adr[14:2]}
|
wb_xrom_adr[12:0]}
|
|
),
|
),
|
|
|
.wbd_be_slave ({reg_uart_be,
|
.wbd_be_slave ({reg_uart_be,
|
reg_spi_be,
|
reg_spi_be,
|
wb_xram_be,
|
wb_xram_be }
|
wb_xrom_be}
|
|
),
|
),
|
|
|
.wbd_we_slave ({reg_uart_wr,
|
.wbd_we_slave ({reg_uart_wr,
|
reg_spi_wr,
|
reg_spi_wr,
|
wb_xram_wr,
|
wb_xram_wr
|
wb_xrom_wr
|
|
}),
|
}),
|
|
|
.wbd_ack_slave ({reg_uart_ack,
|
.wbd_ack_slave ({reg_uart_ack,
|
reg_spi_ack,
|
reg_spi_ack,
|
wb_xram_ack,
|
wb_xram_ack
|
wb_xrom_ack
|
|
}),
|
}),
|
.wbd_stb_slave ({reg_uart_cs,
|
.wbd_stb_slave ({reg_uart_cs,
|
reg_spi_cs,
|
reg_spi_cs,
|
wb_xram_stb,
|
wb_xram_stb
|
wb_xrom_stb
|
|
}),
|
}),
|
|
|
.wbd_cyc_slave (),
|
.wbd_cyc_slave (),
|
.wbd_err_slave (),
|
.wbd_err_slave (),
|
.wbd_rty_slave ()
|
.wbd_rty_slave ()
|
| Line 541... |
Line 493... |
`endif
|
`endif
|
// external access (active low)
|
// external access (active low)
|
.ea_in (ea_in )
|
.ea_in (ea_in )
|
);
|
);
|
|
|
|
//
|
|
// external data ram
|
|
//
|
|
oc8051_xram oc8051_xram1 (
|
|
.clk (app_clk ),
|
|
.rst (!reset_n ),
|
|
.wr (wb_xram_wr ),
|
|
.be (wb_xram_be ),
|
|
.addr (wb_xram_adr ),
|
|
.data_in (wb_xram_wdata ),
|
|
.data_out (wb_xram_rdata ),
|
|
.ack (wb_xram_ack ),
|
|
.stb (wb_xram_stb )
|
|
);
|
|
|
|
|
|
defparam oc8051_xram1.DELAY = 2;
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
