| Line 27... |
Line 27... |
// 1. Bus interface is changed from 32 bit to 8 bit
|
// 1. Bus interface is changed from 32 bit to 8 bit
|
// v0.3 - Dinesh A, 21 Dec 2016
|
// v0.3 - Dinesh A, 21 Dec 2016
|
// 1. Uart Message Handler is integrated
|
// 1. Uart Message Handler is integrated
|
// 2. Message handler is connected as Register Master to
|
// 2. Message handler is connected as Register Master to
|
// Inter-connect
|
// Inter-connect
|
|
// v0.4 - Dinesh A, 6th Jan 2017
|
|
// 1. I2C Master Core is integrated
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
| Line 57... |
Line 59... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
`include "top_defines.v"
|
`include "top_defines.v"
|
module digital_core (
|
module digital_core (
|
|
|
reset_n ,
|
aresetn ,
|
scan_mode ,
|
scan_mode ,
|
scan_enable ,
|
scan_enable ,
|
fastsim_mode ,
|
fastsim_mode ,
|
mastermode ,
|
mastermode ,
|
xtal_clk ,
|
xtal_clk ,
|
| Line 90... |
Line 92... |
uart1_rxd ,
|
uart1_rxd ,
|
|
|
spi_sck ,
|
spi_sck ,
|
spi_so ,
|
spi_so ,
|
spi_si ,
|
spi_si ,
|
spi_cs_n
|
spi_cs_n ,
|
|
|
|
|
|
|
|
// i2cm clock line
|
|
i2cm_scl_i ,
|
|
i2cm_scl_o ,
|
|
i2cm_scl_oen ,
|
|
|
|
// i2cm data line
|
|
i2cm_sda_i ,
|
|
i2cm_sda_o ,
|
|
i2cm_sda_oen
|
|
|
|
|
);
|
);
|
|
|
|
|
//----------------------------------------
|
//----------------------------------------
|
// Global Clock Defination
|
// Global Clock Defination
|
//----------------------------------------
|
//----------------------------------------
|
input reset_n ; // Active Low Reset
|
input aresetn ; // Async Active Low Reset
|
input scan_mode ; // scan mode
|
input scan_mode ; // scan mode
|
input scan_enable ; // scan enable
|
input scan_enable ; // scan enable
|
input fastsim_mode ; // Fast Sim Mode
|
input fastsim_mode ; // Fast Sim Mode
|
input mastermode ; // 1 : Risc master mode
|
input mastermode ; // 1 : Risc master mode
|
input ea_in ; // input for external access (ea signal)
|
input ea_in ; // input for external access (ea signal)
|
| Line 148... |
Line 157... |
output spi_sck ; // clock
|
output spi_sck ; // clock
|
output spi_so ; // data out
|
output spi_so ; // data out
|
input spi_si ; // data in
|
input spi_si ; // data in
|
output [3:0] spi_cs_n ; // chip select
|
output [3:0] spi_cs_n ; // chip select
|
|
|
|
//----------------------------------------
|
|
// i2cm clock line
|
|
//----------------------------------------
|
|
input i2cm_scl_i ;
|
|
output i2cm_scl_o ;
|
|
output i2cm_scl_oen ;
|
|
|
|
//----------------------------------------
|
|
// i2cm data line
|
|
//----------------------------------------
|
|
input i2cm_sda_i ;
|
|
output i2cm_sda_o ;
|
|
output i2cm_sda_oen ;
|
|
|
//----------------------------------------
|
//----------------------------------------
|
// 8051 core RAM related signals
|
// 8051 core RAM related signals
|
//---------------------------------------
|
//---------------------------------------
|
wire [15:0] wb_xram_adr ; // data-ram address
|
wire [15:0] wb_xram_adr ; // data-ram address
|
| Line 162... |
Line 184... |
wire [7:0] wb_xram_wdata ; // ram data input
|
wire [7:0] wb_xram_wdata ; // ram data input
|
|
|
wire wb_xram_stb ; // data-ram strobe
|
wire wb_xram_stb ; // data-ram strobe
|
wire wb_xram_cyc ; // data-ram cycle
|
wire wb_xram_cyc ; // data-ram cycle
|
|
|
|
//----------------------------------------
|
|
// i2CM Wishbone I/F
|
|
//---------------------------------------
|
|
wire [15:0] wb_i2cm_addr ; // data-ram address
|
|
wire wb_i2cm_ack ; // data-ram acknowlage
|
|
wire wb_i2cm_err ; // data-ram error
|
|
wire wb_i2cm_we ; // data-ram error
|
|
wire [7:0] wb_i2cm_rdata ; // ram data input
|
|
wire [7:0] wb_i2cm_wdata ; // ram data input
|
|
|
|
wire wb_i2cm_stb ; // data-ram strobe
|
|
wire wb_i2cm_cyc ; // data-ram cycle
|
|
|
//----------------------------------------
|
//----------------------------------------
|
// Message Controller Reg Master
|
// Message Controller Reg Master
|
//---------------------------------------
|
//---------------------------------------
|
wire mh_reg_cs ;
|
wire mh_reg_cs ;
|
| Line 221... |
Line 255... |
|
|
//-------------------------------------------
|
//-------------------------------------------
|
// clock-gen instantiation
|
// clock-gen instantiation
|
//-------------------------------------------
|
//-------------------------------------------
|
clkgen u_clkgen (
|
clkgen u_clkgen (
|
. reset_n (reset_n ),
|
. aresetn (aresetn ),
|
. fastsim_mode (fastsim_mode ),
|
. fastsim_mode (fastsim_mode ),
|
. mastermode (mastermode ),
|
. mastermode (mastermode ),
|
. xtal_clk (xtal_clk ),
|
. xtal_clk (xtal_clk ),
|
. clkout (clkout ),
|
. clkout (clkout ),
|
. gen_resetn (gen_resetn ),
|
. gen_resetn (gen_resetn ),
|
| Line 236... |
Line 270... |
);
|
);
|
|
|
/************* Message Handler **********/
|
/************* Message Handler **********/
|
|
|
msg_handler_top u_msg_hand_top (
|
msg_handler_top u_msg_hand_top (
|
. line_reset_n (reset_n ),
|
. line_reset_n (aresetn ),
|
. line_clk (app_clk ),
|
. line_clk (app_clk ),
|
|
|
// Towards Register Interface
|
// Towards Register Interface
|
. reg_addr (mh_reg_addr ),
|
. reg_addr (mh_reg_addr ),
|
. reg_wr (mh_reg_wr ),
|
. reg_wr (mh_reg_wr ),
|
| Line 272... |
Line 306... |
//------------------------------
|
//------------------------------
|
// 8051 Data Memory Map
|
// 8051 Data Memory Map
|
// 0x0000 to 0x7FFFF - Data Memory
|
// 0x0000 to 0x7FFFF - Data Memory
|
// 0x8000 to 0x8FFF - SPI
|
// 0x8000 to 0x8FFF - SPI
|
// 0x9000 to 0x9FFF - UART
|
// 0x9000 to 0x9FFF - UART
|
|
// 0xA000 to 0xAFFF - I2CM
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
// Target ID Mapping
|
// Target ID Mapping
|
|
// 4'b0011 -- I2CM
|
// 4'b0010 -- UART
|
// 4'b0010 -- UART
|
// 4'b0001 -- SPI core
|
// 4'b0001 -- SPI core
|
// 4'b0000 -- External RAM
|
// 4'b0000 -- External RAM
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
//
|
//
|
wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :
|
wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :
|
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
|
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
|
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
|
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 :
|
|
(wbd_risc_adr[15:12] == 4'b1010 ) ? 4'b0011 : 4'b0000;
|
|
|
wire [3:0] mh_tar_id = (mh_reg_addr[15] == 1'b0 ) ? 4'b0000 :
|
wire [3:0] mh_tar_id = (mh_reg_addr[15] == 1'b0 ) ? 4'b0000 :
|
(mh_reg_addr[15:12] == 4'b1000 ) ? 4'b0001 :
|
(mh_reg_addr[15:12] == 4'b1000 ) ? 4'b0001 :
|
(mh_reg_addr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
|
(mh_reg_addr[15:12] == 4'b1001 ) ? 4'b0010 :
|
|
(mh_reg_addr[15:12] == 4'b1010 ) ? 4'b0011 : 4'b0000;
|
|
|
wb_crossbar #(.WB_MASTER(3),
|
wb_crossbar #(.WB_MASTER(3),
|
.WB_SLAVE(3),
|
.WB_SLAVE(4),
|
.D_WD(8),
|
.D_WD(8),
|
.BE_WD(1),
|
.BE_WD(1),
|
.ADR_WD(15),
|
.ADR_WD(15),
|
.TAR_WD(4))
|
.TAR_WD(4))
|
u_wb_crossbar (
|
u_wb_crossbar (
|
| Line 339... |
Line 377... |
|
|
.wbd_err_master (),
|
.wbd_err_master (),
|
.wbd_rty_master (),
|
.wbd_rty_master (),
|
|
|
// Slave Interface Signal
|
// Slave Interface Signal
|
.wbd_din_slave ({reg_uart_wdata,
|
.wbd_din_slave ({wb_i2cm_wdata,
|
|
reg_uart_wdata,
|
reg_spi_wdata,
|
reg_spi_wdata,
|
wb_xram_wdata
|
wb_xram_wdata
|
}),
|
}),
|
|
|
.wbd_dout_slave ({reg_uart_rdata,
|
.wbd_dout_slave ({wb_i2cm_rdata,
|
|
reg_uart_rdata,
|
reg_spi_rdata,
|
reg_spi_rdata,
|
wb_xram_rdata
|
wb_xram_rdata
|
}),
|
}),
|
|
|
.wbd_adr_slave ({reg_uart_addr[14:0],
|
.wbd_adr_slave ({wb_i2cm_addr[14:0],
|
|
reg_uart_addr[14:0],
|
reg_spi_addr[14:0],
|
reg_spi_addr[14:0],
|
wb_xram_adr[14:0]}
|
wb_xram_adr[14:0]
|
|
}
|
),
|
),
|
|
|
.wbd_be_slave (),
|
.wbd_be_slave (),
|
|
|
.wbd_we_slave ({reg_uart_wr,
|
.wbd_we_slave ({wb_i2cm_we,
|
|
reg_uart_wr,
|
reg_spi_wr,
|
reg_spi_wr,
|
wb_xram_wr
|
wb_xram_wr
|
}),
|
}),
|
|
|
.wbd_ack_slave ({reg_uart_ack,
|
.wbd_ack_slave ({wb_i2cm_ack,
|
|
reg_uart_ack,
|
reg_spi_ack,
|
reg_spi_ack,
|
wb_xram_ack
|
wb_xram_ack
|
}),
|
}),
|
.wbd_stb_slave ({reg_uart_cs,
|
.wbd_stb_slave ({wb_i2cm_stb,
|
|
reg_uart_cs,
|
reg_spi_cs,
|
reg_spi_cs,
|
wb_xram_stb
|
wb_xram_stb
|
|
|
}),
|
}),
|
|
|
.wbd_cyc_slave (),
|
.wbd_cyc_slave ({wb_i2cm_cyc,
|
|
wb_uart_cyc,
|
|
wb_spi_cyc,
|
|
wb_xram_cyc
|
|
}),
|
.wbd_err_slave (),
|
.wbd_err_slave (),
|
.wbd_rty_slave ()
|
.wbd_rty_slave ()
|
);
|
);
|
|
|
|
|
| Line 437... |
Line 487... |
. si (spi_si ),
|
. si (spi_si ),
|
. cs_n (spi_cs_n )
|
. cs_n (spi_cs_n )
|
|
|
);
|
);
|
|
|
|
/******************************************************
|
|
* I2C Master Core
|
|
* ***************************************************/
|
|
i2cm_top i_i2cm (
|
|
// wishbone signals
|
|
.wb_clk_i (app_clk ),
|
|
.sresetn (gen_resetn ),
|
|
.aresetn (aresetn ),
|
|
.wb_adr_i (wb_i2cm_addr[2:0] ),
|
|
.wb_dat_i (wb_i2cm_wdata ),
|
|
.wb_dat_o (wb_i2cm_rdata ),
|
|
.wb_we_i (wb_i2cm_we ),
|
|
.wb_stb_i (wb_i2cm_stb ),
|
|
.wb_cyc_i (wb_i2cm_cyc ),
|
|
.wb_ack_o (wb_i2cm_ack ),
|
|
.wb_inta_o (i2cm_inta ),
|
|
|
|
// I2C signals
|
|
// i2c clock line
|
|
.scl_pad_i (i2cm_scl_i ),
|
|
.scl_pad_o (i2cm_scl_o ),
|
|
.scl_padoen_o (i2cm_scl_oen ),
|
|
|
|
// i2c data line
|
|
.sda_pad_i (i2cm_sda_i ),
|
|
.sda_pad_o (i2cm_sda_o ),
|
|
.sda_padoen_o (i2cm_sda_oen )
|
|
|
|
);
|
|
|
|
|
|
|
|
/******************************************************
|
|
* 8051 Core
|
|
*******************************************************/
|
|
|
oc8051_top u_8051_core (
|
oc8051_top u_8051_core (
|
. resetn (risc_resetn ),
|
. resetn (risc_resetn ),
|
. wb_clk_i (app_clk ),
|
. wb_clk_i (app_clk ),
|
|
|
| Line 515... |
Line 599... |
//
|
//
|
// external data ram
|
// external data ram
|
//
|
//
|
oc8051_xram oc8051_xram1 (
|
oc8051_xram oc8051_xram1 (
|
.clk (app_clk ),
|
.clk (app_clk ),
|
.rst (!reset_n ),
|
.rst (!aresetn ),
|
.wr (wb_xram_wr ),
|
.wr (wb_xram_wr ),
|
.addr (wb_xram_adr ),
|
.addr (wb_xram_adr ),
|
.data_in (wb_xram_wdata ),
|
.data_in (wb_xram_wdata ),
|
.data_out (wb_xram_rdata ),
|
.data_out (wb_xram_rdata ),
|
.ack (wb_xram_ack ),
|
.ack (wb_xram_ack ),
|
