| Line 17... |
Line 17... |
//// -Dinesh Annayya, dinesha@opencores.org ////
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//// -Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Jan 6, 2017 ////
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//// Revision : Jan 6, 2017 ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// v0.0 - Dinesh A, 6th Jan 2017
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//// v0.0 - Dinesh A, 6th Jan 2017
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// 1. Initail version picked from
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//// 1. Initail version picked from
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// http://www.opencores.org/projects/i2c/
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//// http://www.opencores.org/projects/i2c/
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// 2. renaming of reset signal to aresetn and sresetn
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//// 2. renaming of reset signal to aresetn and sresetn
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//
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//// v0.1 - Dinesh.A, 19th Jan 2017
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//// 1. Lint Error fixes
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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| Line 149... |
Line 150... |
assign dout = sr;
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assign dout = sr;
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// generate shift register
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// generate shift register
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always @(posedge clk or negedge aresetn)
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always @(posedge clk or negedge aresetn)
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if (!aresetn)
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if (!aresetn)
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sr <= #1 8'h0;
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sr <= 8'h0;
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else if (!sresetn)
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else if (!sresetn)
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sr <= #1 8'h0;
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sr <= 8'h0;
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else if (ld)
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else if (ld)
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sr <= #1 din;
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sr <= din;
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else if (shift)
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else if (shift)
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sr <= #1 {sr[6:0], core_rxd};
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sr <= {sr[6:0], core_rxd};
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// generate counter
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// generate counter
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always @(posedge clk or negedge aresetn)
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always @(posedge clk or negedge aresetn)
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if (!aresetn)
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if (!aresetn)
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dcnt <= #1 3'h0;
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dcnt <= 3'h0;
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else if (!sresetn)
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else if (!sresetn)
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dcnt <= #1 3'h0;
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dcnt <= 3'h0;
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else if (ld)
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else if (ld)
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dcnt <= #1 3'h7;
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dcnt <= 3'h7;
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else if (shift)
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else if (shift)
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dcnt <= #1 dcnt - 3'h1;
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dcnt <= dcnt - 3'h1;
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assign cnt_done = ~(|dcnt);
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assign cnt_done = ~(|dcnt);
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//
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//
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// state machine
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// state machine
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| Line 178... |
Line 179... |
reg [4:0] c_state; // synopsys enum_state
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reg [4:0] c_state; // synopsys enum_state
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always @(posedge clk or negedge aresetn)
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always @(posedge clk or negedge aresetn)
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if (!aresetn)
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if (!aresetn)
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begin
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begin
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core_cmd <= #1 `I2C_CMD_NOP;
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core_cmd <= `I2C_CMD_NOP;
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core_txd <= #1 1'b0;
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core_txd <= 1'b0;
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shift <= #1 1'b0;
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shift <= 1'b0;
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ld <= #1 1'b0;
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ld <= 1'b0;
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cmd_ack <= #1 1'b0;
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cmd_ack <= 1'b0;
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c_state <= #1 ST_IDLE;
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c_state <= ST_IDLE;
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ack_out <= #1 1'b0;
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ack_out <= 1'b0;
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end
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end
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else if (!sresetn | i2c_al)
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else if (!sresetn | i2c_al)
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begin
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begin
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core_cmd <= #1 `I2C_CMD_NOP;
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core_cmd <= `I2C_CMD_NOP;
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core_txd <= #1 1'b0;
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core_txd <= 1'b0;
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shift <= #1 1'b0;
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shift <= 1'b0;
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ld <= #1 1'b0;
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ld <= 1'b0;
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cmd_ack <= #1 1'b0;
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cmd_ack <= 1'b0;
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c_state <= #1 ST_IDLE;
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c_state <= ST_IDLE;
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ack_out <= #1 1'b0;
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ack_out <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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// initially reset all signals
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// initially reset all signals
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core_txd <= #1 sr[7];
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core_txd <= sr[7];
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shift <= #1 1'b0;
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shift <= 1'b0;
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ld <= #1 1'b0;
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ld <= 1'b0;
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cmd_ack <= #1 1'b0;
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cmd_ack <= 1'b0;
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case (c_state) // synopsys full_case parallel_case
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case (c_state) // synopsys full_case parallel_case
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ST_IDLE:
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ST_IDLE:
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if (go)
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if (go)
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begin
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begin
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if (start)
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if (start)
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begin
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begin
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c_state <= #1 ST_START;
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c_state <= ST_START;
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core_cmd <= #1 `I2C_CMD_START;
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core_cmd <= `I2C_CMD_START;
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end
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end
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else if (read)
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else if (read)
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begin
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begin
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c_state <= #1 ST_READ;
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c_state <= ST_READ;
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core_cmd <= #1 `I2C_CMD_READ;
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core_cmd <= `I2C_CMD_READ;
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end
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end
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else if (write)
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else if (write)
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begin
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begin
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c_state <= #1 ST_WRITE;
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c_state <= ST_WRITE;
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core_cmd <= #1 `I2C_CMD_WRITE;
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core_cmd <= `I2C_CMD_WRITE;
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end
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end
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else // stop
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else // stop
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begin
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begin
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c_state <= #1 ST_STOP;
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c_state <= ST_STOP;
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core_cmd <= #1 `I2C_CMD_STOP;
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core_cmd <= `I2C_CMD_STOP;
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end
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end
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ld <= #1 1'b1;
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ld <= 1'b1;
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end
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end
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ST_START:
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ST_START:
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if (core_ack)
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if (core_ack)
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begin
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begin
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if (read)
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if (read)
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begin
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begin
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c_state <= #1 ST_READ;
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c_state <= ST_READ;
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core_cmd <= #1 `I2C_CMD_READ;
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core_cmd <= `I2C_CMD_READ;
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end
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end
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else
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else
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begin
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begin
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c_state <= #1 ST_WRITE;
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c_state <= ST_WRITE;
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core_cmd <= #1 `I2C_CMD_WRITE;
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core_cmd <= `I2C_CMD_WRITE;
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end
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end
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ld <= #1 1'b1;
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ld <= 1'b1;
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end
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end
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ST_WRITE:
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ST_WRITE:
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if (core_ack)
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if (core_ack)
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if (cnt_done)
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if (cnt_done)
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begin
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begin
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c_state <= #1 ST_ACK;
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c_state <= ST_ACK;
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core_cmd <= #1 `I2C_CMD_READ;
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core_cmd <= `I2C_CMD_READ;
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end
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end
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else
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else
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begin
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begin
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c_state <= #1 ST_WRITE; // stay in same state
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c_state <= ST_WRITE; // stay in same state
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core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
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core_cmd <= `I2C_CMD_WRITE; // write next bit
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shift <= #1 1'b1;
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shift <= 1'b1;
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end
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end
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ST_READ:
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ST_READ:
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if (core_ack)
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if (core_ack)
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begin
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begin
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if (cnt_done)
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if (cnt_done)
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begin
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begin
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c_state <= #1 ST_ACK;
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c_state <= ST_ACK;
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core_cmd <= #1 `I2C_CMD_WRITE;
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core_cmd <= `I2C_CMD_WRITE;
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end
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end
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else
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else
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begin
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begin
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c_state <= #1 ST_READ; // stay in same state
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c_state <= ST_READ; // stay in same state
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core_cmd <= #1 `I2C_CMD_READ; // read next bit
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core_cmd <= `I2C_CMD_READ; // read next bit
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end
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end
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|
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shift <= #1 1'b1;
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shift <= 1'b1;
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core_txd <= #1 ack_in;
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core_txd <= ack_in;
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end
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end
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ST_ACK:
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ST_ACK:
|
if (core_ack)
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if (core_ack)
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begin
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begin
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if (stop)
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if (stop)
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begin
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begin
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c_state <= #1 ST_STOP;
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c_state <= ST_STOP;
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core_cmd <= #1 `I2C_CMD_STOP;
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core_cmd <= `I2C_CMD_STOP;
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end
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end
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else
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else
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begin
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begin
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c_state <= #1 ST_IDLE;
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c_state <= ST_IDLE;
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core_cmd <= #1 `I2C_CMD_NOP;
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core_cmd <= `I2C_CMD_NOP;
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// generate command acknowledge signal
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// generate command acknowledge signal
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cmd_ack <= #1 1'b1;
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cmd_ack <= 1'b1;
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end
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end
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|
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// assign ack_out output to bit_controller_rxd (contains last received bit)
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// assign ack_out output to bit_controller_rxd (contains last received bit)
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ack_out <= #1 core_rxd;
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ack_out <= core_rxd;
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|
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core_txd <= #1 1'b1;
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core_txd <= 1'b1;
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end
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end
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else
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else
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core_txd <= #1 ack_in;
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core_txd <= ack_in;
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|
|
ST_STOP:
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ST_STOP:
|
if (core_ack)
|
if (core_ack)
|
begin
|
begin
|
c_state <= #1 ST_IDLE;
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c_state <= ST_IDLE;
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core_cmd <= #1 `I2C_CMD_NOP;
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core_cmd <= `I2C_CMD_NOP;
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// generate command acknowledge signal
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// generate command acknowledge signal
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cmd_ack <= #1 1'b1;
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cmd_ack <= 1'b1;
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end
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end
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default: c_state <= ST_IDLE;
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|
|
endcase
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endcase
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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