Line 252... |
Line 252... |
reg [WB_SLAVE-1:0] slave_busy; // slave busy flag
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reg [WB_SLAVE-1:0] slave_busy; // slave busy flag
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reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0];
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reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0];
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reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0];
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reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0];
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reg [TAR_WD-1 :0] cur_target_id;
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reg [TAR_WD-1 :0] cur_target_id;
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wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER:0]; // target address from master
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wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master
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wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master
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wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master
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reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master
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reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master
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wire [ADR_WD-1:0] wbd_adr_master_t[WB_MASTER-1:0]; // target address from master
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wire [ADR_WD-1:0] wbd_adr_master_t[WB_MASTER-1:0]; // target address from master
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wire [BE_WD-1:0] wbd_be_master_t[WB_MASTER-1:0]; // target address from master
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wire [BE_WD-1:0] wbd_be_master_t[WB_MASTER-1:0]; // target address from master
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Line 351... |
Line 351... |
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*********************************************************/
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*********************************************************/
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always @(negedge rst_n or posedge clk) begin
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always @(negedge rst_n or posedge clk) begin
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if(rst_n == 0) begin
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if(rst_n == 0) begin
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master_busy = 0;
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master_busy <= 0;
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slave_busy = 0;
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slave_busy <= 0;
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cur_target_id = 0;
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end else begin
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end
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else begin
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for(i = 0; i < WB_MASTER; i = i + 1) begin
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for(i = 0; i < WB_MASTER; i = i + 1) begin
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cur_target_id = wbd_taddr_master_t[i];
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cur_target_id = wbd_taddr_master_t[i];
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if(master_busy[i] == 0) begin
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if(master_busy[i] == 0) begin
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if(wbd_stb_master[i] & slave_busy[cur_target_id] == 0) begin
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if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
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master_mx_id[i] <= cur_target_id;
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master_mx_id[i] <= wbd_taddr_master_t[i];
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slave_mx_id [cur_target_id] = i;
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slave_mx_id [wbd_taddr_master_t[i]] <= i;
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slave_busy[cur_target_id] = 1;
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slave_busy[wbd_taddr_master_t[i]] <= 1;
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master_busy[i] = 1;
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master_busy[i] <= 1;
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// synopsys translate_off
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// synopsys translate_off
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// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,cur_target_id);
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// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
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// synopsys translate_on
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// synopsys translate_on
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end
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end
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end else if(wbd_cyc_master[i] == 0) begin
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end else if(wbd_cyc_master[i] == 0) begin
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master_busy[i] = 0;
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if(master_busy[i] == 1) begin
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slave_busy[cur_target_id] = 0;
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// synopsys translate_off
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// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
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// synopsys translate_on
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end
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master_busy[i] <= 0;
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slave_busy[wbd_taddr_master_t[i]] <= 0;
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end
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end
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end
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end
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end
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end
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end
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end
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