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//////////////////////////////////////////////////////////////////////
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//// ////
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//// UART Message Handler Module ////
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//// ////
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//// This file is part of the oms8051mini cores project ////
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//// http://www.opencores.org/cores/oms8051min/ ////
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//// ////
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//// Description ////
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//// Uart Message Handler definitions. ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// Revision: ////
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//// v-0: 27 Nov 2016 ////
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//// A. rtl file picked from ////
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//// http://www.opencores.org/cores/uart2spi/ ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module msg_handler (
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reset_n ,
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sys_clk ,
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// UART-TX Information
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tx_data_avail,
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tx_rd,
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tx_data,
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// UART-RX Information
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rx_ready,
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rx_wr,
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rx_data,
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// Towards Register Interface
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reg_addr,
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reg_wr,
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reg_wdata,
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reg_req,
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reg_ack,
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reg_rdata
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);
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// Define the Message Hanlde States
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`define IDLE 4'h0
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`define IDLE_TX_MSG1 4'h1
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`define IDLE_TX_MSG2 4'h2
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`define RX_CMD_PHASE 4'h3
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`define WR_ADR_PHASE 4'h4
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`define WR_DATA_PHASE 4'h5
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`define SEND_WR_REQ 4'h6
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`define RD_ADDR_PHASE 4'h7
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`define SEND_RD_REQ 4'h8
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`define SEND_RD_DATA 4'h9
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`define TX_MSG 4'hA
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`define BREAK_CHAR 8'h0A
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//---------------------------------
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// Global Dec
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// ---------------------------------
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input reset_n ; // line reset
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input sys_clk ; // line clock
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//--------------------------------------
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// UART TXD Path
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// -------------------------------------
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output tx_data_avail ; // Indicate valid TXD Data available
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output [7:0] tx_data ; // TXD Data to be transmited
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input tx_rd ; // Indicate TXD Data Been Read
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//--------------------------------------
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// UART RXD Path
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// -------------------------------------
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output rx_ready ; // Indicate Ready to accept the Read Data
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input [7:0] rx_data ; // RXD Data
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input rx_wr ; // Valid RXD Data
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//---------------------------------------
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// Control Unit interface
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// --------------------------------------
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output [15:0] reg_addr ; // Operend-1
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output [7:0] reg_wdata ; // Operend-2
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output reg_req ; // Register Request
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output reg_wr ; // 1 -> write; 0 -> read
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input reg_ack ; // Register Ack
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input [7:0] reg_rdata ;
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// Local Wire/Register Decleration
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//
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//
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reg tx_data_avail ;
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reg [7:0] tx_data ;
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reg [16*8-1:0] TxMsgBuf ; // 16 Byte Tx Message Buffer
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reg [4:0] TxMsgSize ;
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reg [4:0] RxMsgCnt ; // Count the Receive Message Count
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reg [3:0] State ;
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reg [3:0] NextState ;
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reg [15:0] cmd ; // command
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reg [15:0] reg_addr ; // reg_addr
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reg [7:0] reg_wdata ; // reg_addr
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reg reg_wr ; // 1 -> Reg Write request, 0 -> Read Requestion
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reg reg_req ; // 1 -> Register request
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wire rx_ready = 1;
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/****************************************************************
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* UART Message Hanlding Steps
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*
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* 1. On Reset Or Unknown command, Send the Default Message
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* Select Option:
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* wr <addr> <data>
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* rd <addr>
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* 2. Wait for User command <wr/rd>
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* 3. On <wr> command move to write address phase;
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* phase
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* A. After write address phase move to write data phase
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* B. After write data phase, once user press \r command ; send register req
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* and write request and address + data
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* C. On receiving register ack response; send <success> message back and move
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* to state-2
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* 3. On <rd> command move to read address phase;
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* A. After read address phase , once user press '\r' command; send
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* register req , read request
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* C. On receiving register ack response; send <response + read_data> message and move
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* to state-2
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* *****************************************************************/
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always @(negedge reset_n or posedge sys_clk)
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begin
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if(reset_n == 1'b0) begin
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tx_data_avail <= 0;
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reg_req <= 0;
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State <= `IDLE;
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NextState <= `IDLE;
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end else begin
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case(State)
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// Send Default Message
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`IDLE: begin
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TxMsgBuf <= "Command Format:\n"; // Align to 16 character format by appending space character
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TxMsgSize <= 16;
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tx_data_avail <= 0;
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State <= `TX_MSG;
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NextState <= `IDLE_TX_MSG1;
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end
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// Send Default Message (Contd..)
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`IDLE_TX_MSG1: begin
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TxMsgBuf <= "wm <ad> <data>\n "; // Align to 16 character format by appending space character
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TxMsgSize <= 15;
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tx_data_avail <= 0;
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State <= `TX_MSG;
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NextState <= `IDLE_TX_MSG2;
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end
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// Send Default Message (Contd..)
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`IDLE_TX_MSG2: begin
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TxMsgBuf <= "rm <ad>\n>> "; // Align to 16 character format by appending space character
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TxMsgSize <= 10;
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tx_data_avail <= 0;
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RxMsgCnt <= 0;
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State <= `TX_MSG;
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NextState <= `RX_CMD_PHASE;
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end
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// Wait for Response
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`RX_CMD_PHASE: begin
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if(rx_wr == 1) begin
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//if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the same
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if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the same
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//end else if(RxMsgCnt > 0 && rx_data == " ") begin // Check the command
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end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Check the command
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//if(cmd == "wm") begin
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if(cmd == 16'h776D) begin
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RxMsgCnt <= 0;
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reg_addr <= 0;
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reg_wdata <= 0;
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State <= `WR_ADR_PHASE;
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//end else if(cmd == "rm") begin
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end else if(cmd == 16'h726D) begin
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reg_addr <= 0;
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RxMsgCnt <= 0;
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State <= `RD_ADDR_PHASE;
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end else begin // Unknow command
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State <= `IDLE;
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end
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//end else if(rx_data == "\n") begin // Error State
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end else if(rx_data == `BREAK_CHAR) begin // Error State
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State <= `IDLE;
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end
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else begin
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cmd <= (cmd << 8) | rx_data ;
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RxMsgCnt <= RxMsgCnt+1;
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end
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end
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end
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// Write Address Phase
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`WR_ADR_PHASE: begin
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if(rx_wr == 1) begin
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//if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the Space character
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if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the Space character
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//end else if(RxMsgCnt > 0 && rx_data == " ") begin // Move to write data phase
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end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Move to write data phase
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State <= `WR_DATA_PHASE;
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//end else if(rx_data == "\n") begin // Error State
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end else if(rx_data == `BREAK_CHAR) begin // Error State
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State <= `IDLE;
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end else begin
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reg_addr <= (reg_addr << 4) | char2hex(rx_data);
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RxMsgCnt <= RxMsgCnt+1;
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end
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end
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end
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// Write Data Phase
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`WR_DATA_PHASE: begin
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if(rx_wr == 1) begin
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//if(rx_data == " ") begin // Ignore the Space character
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if(rx_data == 8'h20) begin // Ignore the Space character
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//end else if(rx_data == "\n") begin // Error State
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end else if(rx_data == `BREAK_CHAR) begin // Error State
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State <= `SEND_WR_REQ;
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reg_wr <= 1'b1; // Write request
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reg_req <= 1'b1;
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end else begin // A to F
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reg_wdata <= (reg_wdata << 4) | char2hex(rx_data);
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end
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end
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end
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`SEND_WR_REQ: begin
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if(reg_ack) begin
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reg_req <= 1'b0;
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TxMsgBuf <= "cmd success\n>> "; // Align to 16 character format by appending space character
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TxMsgSize <= 14;
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tx_data_avail <= 0;
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State <= `TX_MSG;
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NextState <= `RX_CMD_PHASE;
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end
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end
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// Write Address Phase
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`RD_ADDR_PHASE: begin
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if(rx_wr == 1) begin
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//if(rx_data == " ") begin // Ignore the Space character
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if(rx_data == 8'h20) begin // Ignore the Space character
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//end else if(rx_data == "\n") begin // Error State
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end else if(rx_data == `BREAK_CHAR) begin // Error State
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State <= `SEND_RD_REQ;
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reg_wr <= 1'b0; // Read request
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reg_req <= 1'b1; // Reg Request
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end
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else begin // A to F
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reg_addr <= (reg_addr << 4) | char2hex(rx_data);
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RxMsgCnt <= RxMsgCnt+1;
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end
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end
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end
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`SEND_RD_REQ: begin
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if(reg_ack) begin
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reg_req <= 1'b0;
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TxMsgBuf <= "Response: "; // Align to 16 character format by appending space character
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TxMsgSize <= 10;
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tx_data_avail <= 0;
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State <= `TX_MSG;
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NextState <= `SEND_RD_DATA;
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end
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end
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`SEND_RD_DATA: begin // Wait for Operation Completion
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TxMsgBuf[10*8-1:9*8] <= hex2char(reg_rdata[7:4]);
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TxMsgBuf[9*8-1:8*8] <= hex2char(reg_rdata[3:0]);
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TxMsgBuf[8*8-1:7*8] <= "\n";
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TxMsgSize <= 3;
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tx_data_avail <= 0;
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State <= `TX_MSG;
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NextState <= `RX_CMD_PHASE;
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end
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// Send Default Message (Contd..)
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`TX_MSG: begin
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tx_data_avail <= 1;
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tx_data <= TxMsgBuf[16*8-1:15*8];
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if(TxMsgSize == 0) begin
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tx_data_avail <= 0;
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State <= NextState;
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end else if(tx_rd) begin
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TxMsgBuf <= TxMsgBuf << 8;
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TxMsgSize <= TxMsgSize -1;
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end
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end
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endcase
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end
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end
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// Character to hex number
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function [3:0] char2hex;
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input [7:0] data_in;
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case (data_in)
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8'h30: char2hex = 4'h0; // character '0'
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8'h31: char2hex = 4'h1; // character '1'
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8'h32: char2hex = 4'h2; // character '2'
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8'h33: char2hex = 4'h3; // character '3'
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8'h34: char2hex = 4'h4; // character '4'
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8'h35: char2hex = 4'h5; // character '5'
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8'h36: char2hex = 4'h6; // character '6'
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8'h37: char2hex = 4'h7; // character '7'
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8'h38: char2hex = 4'h8; // character '8'
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8'h39: char2hex = 4'h9; // character '9'
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8'h41: char2hex = 4'hA; // character 'A'
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8'h42: char2hex = 4'hB; // character 'B'
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8'h43: char2hex = 4'hC; // character 'C'
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8'h44: char2hex = 4'hD; // character 'D'
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8'h45: char2hex = 4'hE; // character 'E'
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8'h46: char2hex = 4'hF; // character 'F'
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8'h61: char2hex = 4'hA; // character 'a'
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8'h62: char2hex = 4'hB; // character 'b'
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8'h63: char2hex = 4'hC; // character 'c'
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8'h64: char2hex = 4'hD; // character 'd'
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8'h65: char2hex = 4'hE; // character 'e'
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8'h66: char2hex = 4'hF; // character 'f'
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default : char2hex = 4'hF;
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endcase
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endfunction
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// Hex to Asci Character
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function [7:0] hex2char;
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input [3:0] data_in;
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case (data_in)
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4'h0: hex2char = 8'h30; // character '0'
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4'h1: hex2char = 8'h31; // character '1'
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4'h2: hex2char = 8'h32; // character '2'
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4'h3: hex2char = 8'h33; // character '3'
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4'h4: hex2char = 8'h34; // character '4'
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4'h5: hex2char = 8'h35; // character '5'
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4'h6: hex2char = 8'h36; // character '6'
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4'h7: hex2char = 8'h37; // character '7'
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4'h8: hex2char = 8'h38; // character '8'
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4'h9: hex2char = 8'h39; // character '9'
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4'hA: hex2char = 8'h41; // character 'A'
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4'hB: hex2char = 8'h42; // character 'B'
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4'hC: hex2char = 8'h43; // character 'C'
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4'hD: hex2char = 8'h44; // character 'D'
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4'hE: hex2char = 8'h45; // character 'E'
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4'hF: hex2char = 8'h46; // character 'F'
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endcase
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endfunction
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endmodule
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