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https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
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| Rev 19 |
Rev 36 |
| Line 13... |
Line 13... |
//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// Revision: ////
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//// Revision:
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//// v-0: 27 Nov 2016 ////
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//// v-0.0: 27 Nov 2016
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//// A. rtl file picked from ////
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//// A. rtl file picked from
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//// http://www.opencores.org/cores/uart2spi/ ////
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//// http://www.opencores.org/cores/uart2spi/
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//// v-0.1: 19 Jan 2017
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//// A. Lint warning fixed for case statement
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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| Line 167... |
Line 169... |
if(reset_n == 1'b0) begin
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if(reset_n == 1'b0) begin
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tx_data_avail <= 0;
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tx_data_avail <= 0;
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reg_req <= 0;
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reg_req <= 0;
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State <= `IDLE;
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State <= `IDLE;
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NextState <= `IDLE;
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NextState <= `IDLE;
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TxMsgBuf <= 0;
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TxMsgSize <= 0;
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RxMsgCnt <= 0;
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reg_addr <= 0;
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reg_wdata <= 0;
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reg_wr <= 1'b0;
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reg_req <= 1'b0;
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tx_data <= 0;
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cmd <= 0 ;
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end else begin
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end else begin
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case(State)
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case(State)
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// Send Default Message
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// Send Default Message
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`IDLE: begin
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`IDLE: begin
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TxMsgBuf <= "Command Format:\n"; // Align to 16 character format by appending space character
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TxMsgBuf <= "Command Format:\n"; // Align to 16 character format by appending space character
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| Line 321... |
Line 332... |
end else if(tx_rd) begin
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end else if(tx_rd) begin
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TxMsgBuf <= TxMsgBuf << 8;
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TxMsgBuf <= TxMsgBuf << 8;
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TxMsgSize <= TxMsgSize -1;
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TxMsgSize <= TxMsgSize -1;
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end
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end
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end
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end
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default: begin
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State <= `IDLE;
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NextState <= `IDLE;
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end
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endcase
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endcase
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end
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end
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end
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end
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