| Line 123... |
Line 123... |
// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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//---------------------------------
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//---------------------------------
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input reg_cs ;
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input reg_cs ;
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input reg_wr ;
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input reg_wr ;
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input [3:0] reg_addr ;
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input [3:0] reg_addr ;
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input [31:0] reg_wdata ;
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input [7:0] reg_wdata ;
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input [3:0] reg_be ;
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input reg_be ;
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// Outputs
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// Outputs
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output [31:0] reg_rdata ;
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output [7:0] reg_rdata ;
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output reg_ack ;
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output reg_ack ;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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| Line 139... |
Line 139... |
//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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wire sw_rd_en;
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wire sw_rd_en;
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wire sw_wr_en;
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wire sw_wr_en;
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wire [3:0] sw_addr ; // addressing 16 registers
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wire [3:0] sw_addr ; // addressing 16 registers
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wire [3:0] wr_be ;
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wire wr_be ;
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reg [31:0] reg_rdata ;
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reg [7:0] reg_rdata ;
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reg reg_ack ;
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reg reg_ack ;
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wire [31:0] reg_0; // Software_Reg_0
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wire [7:0] reg_0; // Software_Reg_0
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wire [31:0] reg_1; // Software-Reg_1
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wire [7:0] reg_1; // Software-Reg_1
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wire [31:0] reg_2; // Software-Reg_2
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wire [7:0] reg_2; // Software-Reg_2
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wire [31:0] reg_3; // Software-Reg_3
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wire [7:0] reg_3; // Software-Reg_3
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wire [31:0] reg_4; // Software-Reg_4
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wire [7:0] reg_4; // Software-Reg_4
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wire [31:0] reg_5; // Software-Reg_5
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wire [7:0] reg_5; // Software-Reg_5
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wire [31:0] reg_6; // Software-Reg_6
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wire [7:0] reg_6; // Software-Reg_6
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wire [31:0] reg_7; // Software-Reg_7
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wire [7:0] reg_7; // Software-Reg_7
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wire [31:0] reg_8; // Software-Reg_8
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wire [7:0] reg_8; // Software-Reg_8
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wire [31:0] reg_9; // Software-Reg_9
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wire [7:0] reg_9; // Software-Reg_9
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wire [31:0] reg_10; // Software-Reg_10
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wire [7:0] reg_10; // Software-Reg_10
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wire [31:0] reg_11; // Software-Reg_11
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wire [7:0] reg_11; // Software-Reg_11
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wire [31:0] reg_12; // Software-Reg_12
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wire [7:0] reg_12; // Software-Reg_12
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wire [31:0] reg_13; // Software-Reg_13
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wire [7:0] reg_13; // Software-Reg_13
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wire [31:0] reg_14; // Software-Reg_14
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wire [7:0] reg_14; // Software-Reg_14
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wire [31:0] reg_15; // Software-Reg_15
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wire [7:0] reg_15; // Software-Reg_15
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reg [31:0] reg_out;
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reg [7:0] reg_out;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Main code starts here
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// Main code starts here
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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| Line 183... |
Line 183... |
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always @ (posedge mclk or negedge reset_n)
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always @ (posedge mclk or negedge reset_n)
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begin : preg_out_Seq
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begin : preg_out_Seq
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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begin
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begin
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reg_rdata [31:0] <= 32'h0000_0000;
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reg_rdata [7:0] <= 8'h00;
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reg_ack <= 1'b0;
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reg_ack <= 1'b0;
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end
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end
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else if (sw_rd_en && !reg_ack)
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else if (sw_rd_en && !reg_ack)
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begin
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begin
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reg_rdata [31:0] <= reg_out [31:0];
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reg_rdata [7:0] <= reg_out [7:0];
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reg_ack <= 1'b1;
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reg_ack <= 1'b1;
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end
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end
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else if (sw_wr_en && !reg_ack)
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else if (sw_wr_en && !reg_ack)
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reg_ack <= 1'b1;
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reg_ack <= 1'b1;
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else
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else
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| Line 240... |
Line 240... |
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always @( *)
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always @( *)
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begin : preg_sel_Com
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begin : preg_sel_Com
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reg_out [31:0] = 32'd0;
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reg_out [7:0] = 8'd0;
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case (sw_addr [3:0])
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case (sw_addr [3:0])
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4'b0000 : reg_out [31:0] = reg_0 [31:0];
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4'b0000 : reg_out [7:0] = reg_0 [7:0];
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4'b0001 : reg_out [31:0] = reg_1 [31:0];
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4'b0001 : reg_out [7:0] = reg_1 [7:0];
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4'b0010 : reg_out [31:0] = reg_2 [31:0];
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4'b0010 : reg_out [7:0] = reg_2 [7:0];
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4'b0011 : reg_out [31:0] = reg_3 [31:0];
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4'b0011 : reg_out [7:0] = reg_3 [7:0];
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4'b0100 : reg_out [31:0] = reg_4 [31:0];
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4'b0100 : reg_out [7:0] = reg_4 [7:0];
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4'b0101 : reg_out [31:0] = reg_5 [31:0];
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4'b0101 : reg_out [7:0] = reg_5 [7:0];
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4'b0110 : reg_out [31:0] = reg_6 [31:0];
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4'b0110 : reg_out [7:0] = reg_6 [7:0];
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4'b0111 : reg_out [31:0] = reg_7 [31:0];
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4'b0111 : reg_out [7:0] = reg_7 [7:0];
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4'b1000 : reg_out [31:0] = reg_8 [31:0];
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4'b1000 : reg_out [7:0] = reg_8 [7:0];
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4'b1001 : reg_out [31:0] = reg_9 [31:0];
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4'b1001 : reg_out [7:0] = reg_9 [7:0];
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4'b1010 : reg_out [31:0] = reg_10 [31:0];
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4'b1010 : reg_out [7:0] = reg_10 [7:0];
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4'b1011 : reg_out [31:0] = reg_11 [31:0];
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4'b1011 : reg_out [7:0] = reg_11 [7:0];
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4'b1100 : reg_out [31:0] = reg_12 [31:0];
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4'b1100 : reg_out [7:0] = reg_12 [7:0];
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4'b1101 : reg_out [31:0] = reg_13 [31:0];
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4'b1101 : reg_out [7:0] = reg_13 [7:0];
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4'b1110 : reg_out [31:0] = reg_14 [31:0];
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4'b1110 : reg_out [7:0] = reg_14 [7:0];
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4'b1111 : reg_out [31:0] = reg_15 [31:0];
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4'b1111 : reg_out [7:0] = reg_15 [7:0];
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endcase
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endcase
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end
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end
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| Line 276... |
Line 276... |
wire cfg_rx_enable = reg_0[1]; // Rx Enable
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wire cfg_rx_enable = reg_0[1]; // Rx Enable
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wire cfg_tx_enable = reg_0[0]; // Tx Enable
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wire cfg_tx_enable = reg_0[0]; // Tx Enable
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generic_register #(5,0 ) u_uart_ctrl_be0 (
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generic_register #(5,0 ) u_uart_ctrl_be0 (
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.we ({5{sw_wr_en_0 &
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.we ({5{sw_wr_en_0 &
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wr_be[0] }} ),
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wr_be }} ),
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.data_in (reg_wdata[4:0] ),
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.data_in (reg_wdata[4:0] ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.clk (mclk ),
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.clk (mclk ),
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//List of Outs
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//List of Outs
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.data_out (reg_0[4:0] )
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.data_out (reg_0[4:0] )
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);
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);
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assign reg_0[31:5] = 27'h0;
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assign reg_0[7:5] = 3'h0;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Logic for Register 1 : uart interrupt status
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// Logic for Register 1 : uart interrupt status
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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stat_register u_intr_bit0 (
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stat_register u_intr_bit0 (
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//inputs
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//inputs
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. clk (mclk ),
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. clk (mclk ),
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. reset_n (reset_n ),
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. reset_n (reset_n ),
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. cpu_we (sw_wr_en_1 &
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. cpu_we (sw_wr_en_1 &
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wr_be[0] ),
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wr_be ),
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. cpu_ack (reg_wdata[0] ),
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. cpu_ack (reg_wdata[0] ),
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. hware_req (frm_error_o ),
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. hware_req (frm_error_o ),
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//outputs
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//outputs
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. data_out (reg_1[0] )
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. data_out (reg_1[0] )
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| Line 309... |
Line 309... |
stat_register u_intr_bit1 (
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stat_register u_intr_bit1 (
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//inputs
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//inputs
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. clk (mclk ),
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. clk (mclk ),
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. reset_n (reset_n ),
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. reset_n (reset_n ),
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. cpu_we (sw_wr_en_1 &
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. cpu_we (sw_wr_en_1 &
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wr_be[0] ),
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wr_be ),
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. cpu_ack (reg_wdata[1] ),
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. cpu_ack (reg_wdata[1] ),
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. hware_req (par_error_o ),
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. hware_req (par_error_o ),
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//outputs
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//outputs
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. data_out (reg_1[1] )
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. data_out (reg_1[1] )
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| Line 322... |
Line 322... |
stat_register u_intr_bit2 (
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stat_register u_intr_bit2 (
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//inputs
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//inputs
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. clk (mclk ),
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. clk (mclk ),
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. reset_n (reset_n ),
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. reset_n (reset_n ),
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. cpu_we (sw_wr_en_1 &
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. cpu_we (sw_wr_en_1 &
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wr_be[0] ),
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wr_be ),
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. cpu_ack (reg_wdata[2] ),
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. cpu_ack (reg_wdata[2] ),
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. hware_req (rx_fifo_full_err_o ),
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. hware_req (rx_fifo_full_err_o ),
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//outputs
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//outputs
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. data_out (reg_1[2] )
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. data_out (reg_1[2] )
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);
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);
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assign reg_1[31:3] = 29'h0;
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assign reg_1[7:3] = 5'h0;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Logic for Register 2 : Baud Rate Control
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// Logic for Register 2 : Baud Rate Control
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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wire [11:0] cfg_baud_16x = reg_2[11:0];
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wire [11:0] cfg_baud_16x = {reg_3[3:0],reg_2[7:0]};
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generic_register #(12,0 ) u_uart_ctrl_reg2 (
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generic_register #(8,0 ) u_uart_ctrl_reg2 (
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.we ({12{sw_wr_en_2 &
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.we ({8{sw_wr_en_2 &
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wr_be[0] }} ),
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wr_be }} ),
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.data_in (reg_wdata[11:0] ),
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.data_in (reg_wdata[7:0] ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.clk (mclk ),
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.clk (mclk ),
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//List of Outs
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//List of Outs
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.data_out (reg_2[11:0] )
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.data_out (reg_2[7:0] )
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);
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);
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generic_register #(4,0 ) u_uart_ctrl_reg3 (
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.we ({4{sw_wr_en_3 &
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wr_be }} ),
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.data_in (reg_wdata[3:0] ),
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.reset_n (reset_n ),
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.clk (mclk ),
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assign reg_2[31:12] = 20'h0;
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//List of Outs
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.data_out (reg_3[3:0] )
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);
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assign reg_3[7:4] = 4'h0;
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assign reg_3[31:0] = {30'h0,rx_fifo_empty,tx_fifo_full};
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// reg-4 status
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//
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assign reg_4[7:0] = {6'h0,rx_fifo_empty,tx_fifo_full};
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// reg_4 is tx_fifo wr
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// reg_5 is tx_fifo wr
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assign tx_fifo_wr_en = sw_wr_en_4 & reg_ack;
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assign tx_fifo_wr_en = sw_wr_en_5 & reg_ack & !tx_fifo_full;
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assign tx_fifo_data = reg_wdata[7:0];
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assign tx_fifo_data = reg_wdata[7:0];
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// reg_5 is rx_fifo read
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// reg_6 is rx_fifo read
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// rx_fifo read data
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// rx_fifo read data
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assign reg_5[31:0] = {24'h0,rx_fifo_data};
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assign reg_6[7:0] = {rx_fifo_data};
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assign rx_fifo_rd_en = sw_rd_en_5 & reg_ack;
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assign rx_fifo_rd_en = sw_rd_en_6 & reg_ack & !rx_fifo_empty;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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