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[/] [oms8051mini/] [trunk/] [rtl/] [uart/] [uart_cfg.v] - Diff between revs 7 and 11

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Line 123... Line 123...
// Reg Bus Interface Signal
// Reg Bus Interface Signal
//---------------------------------
//---------------------------------
input             reg_cs         ;
input             reg_cs         ;
input             reg_wr         ;
input             reg_wr         ;
input [3:0]       reg_addr       ;
input [3:0]       reg_addr       ;
input [31:0]      reg_wdata      ;
input [7:0]       reg_wdata      ;
input [3:0]       reg_be         ;
input             reg_be         ;
 
 
// Outputs
// Outputs
output [31:0]     reg_rdata      ;
output [7:0]      reg_rdata      ;
output            reg_ack     ;
output            reg_ack     ;
 
 
 
 
 
 
//-----------------------------------------------------------------------
//-----------------------------------------------------------------------
Line 139... Line 139...
//-----------------------------------------------------------------------
//-----------------------------------------------------------------------
 
 
wire           sw_rd_en;
wire           sw_rd_en;
wire           sw_wr_en;
wire           sw_wr_en;
wire  [3:0]    sw_addr ; // addressing 16 registers
wire  [3:0]    sw_addr ; // addressing 16 registers
wire  [3:0]    wr_be   ;
wire           wr_be   ;
 
 
reg   [31:0]  reg_rdata      ;
reg   [7:0]  reg_rdata      ;
reg           reg_ack     ;
reg           reg_ack     ;
 
 
wire [31:0]    reg_0;  // Software_Reg_0
wire [7:0]    reg_0;  // Software_Reg_0
wire [31:0]    reg_1;  // Software-Reg_1
wire [7:0]    reg_1;  // Software-Reg_1
wire [31:0]    reg_2;  // Software-Reg_2
wire [7:0]    reg_2;  // Software-Reg_2
wire [31:0]    reg_3;  // Software-Reg_3
wire [7:0]    reg_3;  // Software-Reg_3
wire [31:0]    reg_4;  // Software-Reg_4
wire [7:0]    reg_4;  // Software-Reg_4
wire [31:0]    reg_5;  // Software-Reg_5
wire [7:0]    reg_5;  // Software-Reg_5
wire [31:0]    reg_6;  // Software-Reg_6
wire [7:0]    reg_6;  // Software-Reg_6
wire [31:0]    reg_7;  // Software-Reg_7
wire [7:0]    reg_7;  // Software-Reg_7
wire [31:0]    reg_8;  // Software-Reg_8
wire [7:0]    reg_8;  // Software-Reg_8
wire [31:0]    reg_9;  // Software-Reg_9
wire [7:0]    reg_9;  // Software-Reg_9
wire [31:0]    reg_10; // Software-Reg_10
wire [7:0]    reg_10; // Software-Reg_10
wire [31:0]    reg_11; // Software-Reg_11
wire [7:0]    reg_11; // Software-Reg_11
wire [31:0]    reg_12; // Software-Reg_12
wire [7:0]    reg_12; // Software-Reg_12
wire [31:0]    reg_13; // Software-Reg_13
wire [7:0]    reg_13; // Software-Reg_13
wire [31:0]    reg_14; // Software-Reg_14
wire [7:0]    reg_14; // Software-Reg_14
wire [31:0]    reg_15; // Software-Reg_15
wire [7:0]    reg_15; // Software-Reg_15
reg  [31:0]    reg_out;
reg  [7:0]    reg_out;
 
 
//-----------------------------------------------------------------------
//-----------------------------------------------------------------------
// Main code starts here
// Main code starts here
//-----------------------------------------------------------------------
//-----------------------------------------------------------------------
 
 
Line 183... Line 183...
 
 
always @ (posedge mclk or negedge reset_n)
always @ (posedge mclk or negedge reset_n)
begin : preg_out_Seq
begin : preg_out_Seq
   if (reset_n == 1'b0)
   if (reset_n == 1'b0)
   begin
   begin
      reg_rdata [31:0]  <= 32'h0000_0000;
      reg_rdata [7:0]  <= 8'h00;
      reg_ack           <= 1'b0;
      reg_ack           <= 1'b0;
   end
   end
   else if (sw_rd_en && !reg_ack)
   else if (sw_rd_en && !reg_ack)
   begin
   begin
      reg_rdata [31:0]  <= reg_out [31:0];
      reg_rdata [7:0]  <= reg_out [7:0];
      reg_ack           <= 1'b1;
      reg_ack           <= 1'b1;
   end
   end
   else if (sw_wr_en && !reg_ack)
   else if (sw_wr_en && !reg_ack)
      reg_ack           <= 1'b1;
      reg_ack           <= 1'b1;
   else
   else
Line 240... Line 240...
 
 
 
 
always @( *)
always @( *)
begin : preg_sel_Com
begin : preg_sel_Com
 
 
  reg_out [31:0] = 32'd0;
  reg_out [7:0] = 8'd0;
 
 
  case (sw_addr [3:0])
  case (sw_addr [3:0])
    4'b0000 : reg_out [31:0] = reg_0 [31:0];
    4'b0000 : reg_out [7:0] = reg_0 [7:0];
    4'b0001 : reg_out [31:0] = reg_1 [31:0];
    4'b0001 : reg_out [7:0] = reg_1 [7:0];
    4'b0010 : reg_out [31:0] = reg_2 [31:0];
    4'b0010 : reg_out [7:0] = reg_2 [7:0];
    4'b0011 : reg_out [31:0] = reg_3 [31:0];
    4'b0011 : reg_out [7:0] = reg_3 [7:0];
    4'b0100 : reg_out [31:0] = reg_4 [31:0];
    4'b0100 : reg_out [7:0] = reg_4 [7:0];
    4'b0101 : reg_out [31:0] = reg_5 [31:0];
    4'b0101 : reg_out [7:0] = reg_5 [7:0];
    4'b0110 : reg_out [31:0] = reg_6 [31:0];
    4'b0110 : reg_out [7:0] = reg_6 [7:0];
    4'b0111 : reg_out [31:0] = reg_7 [31:0];
    4'b0111 : reg_out [7:0] = reg_7 [7:0];
    4'b1000 : reg_out [31:0] = reg_8 [31:0];
    4'b1000 : reg_out [7:0] = reg_8 [7:0];
    4'b1001 : reg_out [31:0] = reg_9 [31:0];
    4'b1001 : reg_out [7:0] = reg_9 [7:0];
    4'b1010 : reg_out [31:0] = reg_10 [31:0];
    4'b1010 : reg_out [7:0] = reg_10 [7:0];
    4'b1011 : reg_out [31:0] = reg_11 [31:0];
    4'b1011 : reg_out [7:0] = reg_11 [7:0];
    4'b1100 : reg_out [31:0] = reg_12 [31:0];
    4'b1100 : reg_out [7:0] = reg_12 [7:0];
    4'b1101 : reg_out [31:0] = reg_13 [31:0];
    4'b1101 : reg_out [7:0] = reg_13 [7:0];
    4'b1110 : reg_out [31:0] = reg_14 [31:0];
    4'b1110 : reg_out [7:0] = reg_14 [7:0];
    4'b1111 : reg_out [31:0] = reg_15 [31:0];
    4'b1111 : reg_out [7:0] = reg_15 [7:0];
  endcase
  endcase
end
end
 
 
 
 
 
 
Line 276... Line 276...
wire         cfg_rx_enable   = reg_0[1];   // Rx Enable
wire         cfg_rx_enable   = reg_0[1];   // Rx Enable
wire         cfg_tx_enable   = reg_0[0];   // Tx Enable
wire         cfg_tx_enable   = reg_0[0];   // Tx Enable
 
 
generic_register #(5,0  ) u_uart_ctrl_be0 (
generic_register #(5,0  ) u_uart_ctrl_be0 (
              .we            ({5{sw_wr_en_0 &
              .we            ({5{sw_wr_en_0 &
                                 wr_be[0]   }}  ),
                                 wr_be   }}  ),
              .data_in       (reg_wdata[4:0]    ),
              .data_in       (reg_wdata[4:0]    ),
              .reset_n       (reset_n           ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
              .clk           (mclk              ),
 
 
              //List of Outs
              //List of Outs
              .data_out      (reg_0[4:0]        )
              .data_out      (reg_0[4:0]        )
          );
          );
 
 
 
 
assign reg_0[31:5] = 27'h0;
assign reg_0[7:5] = 3'h0;
 
 
//-----------------------------------------------------------------------
//-----------------------------------------------------------------------
// Logic for Register 1 : uart interrupt status
// Logic for Register 1 : uart interrupt status
//-----------------------------------------------------------------------
//-----------------------------------------------------------------------
stat_register u_intr_bit0 (
stat_register u_intr_bit0 (
                 //inputs
                 //inputs
                 . clk        (mclk            ),
                 . clk        (mclk            ),
                 . reset_n    (reset_n         ),
                 . reset_n    (reset_n         ),
                 . cpu_we     (sw_wr_en_1 &
                 . cpu_we     (sw_wr_en_1 &
                               wr_be[0]        ),
                               wr_be        ),
                 . cpu_ack    (reg_wdata[0]    ),
                 . cpu_ack    (reg_wdata[0]    ),
                 . hware_req  (frm_error_o     ),
                 . hware_req  (frm_error_o     ),
 
 
                 //outputs
                 //outputs
                 . data_out   (reg_1[0]        )
                 . data_out   (reg_1[0]        )
Line 309... Line 309...
stat_register u_intr_bit1 (
stat_register u_intr_bit1 (
                 //inputs
                 //inputs
                 . clk        (mclk            ),
                 . clk        (mclk            ),
                 . reset_n    (reset_n         ),
                 . reset_n    (reset_n         ),
                 . cpu_we     (sw_wr_en_1 &
                 . cpu_we     (sw_wr_en_1 &
                               wr_be[0]        ),
                               wr_be        ),
                 . cpu_ack    (reg_wdata[1]    ),
                 . cpu_ack    (reg_wdata[1]    ),
                 . hware_req  (par_error_o     ),
                 . hware_req  (par_error_o     ),
 
 
                 //outputs
                 //outputs
                 . data_out   (reg_1[1]        )
                 . data_out   (reg_1[1]        )
Line 322... Line 322...
stat_register u_intr_bit2 (
stat_register u_intr_bit2 (
                 //inputs
                 //inputs
                 . clk        (mclk                ),
                 . clk        (mclk                ),
                 . reset_n    (reset_n             ),
                 . reset_n    (reset_n             ),
                 . cpu_we     (sw_wr_en_1 &
                 . cpu_we     (sw_wr_en_1 &
                               wr_be[0]            ),
                               wr_be            ),
                 . cpu_ack    (reg_wdata[2]        ),
                 . cpu_ack    (reg_wdata[2]        ),
                 . hware_req  (rx_fifo_full_err_o  ),
                 . hware_req  (rx_fifo_full_err_o  ),
 
 
                 //outputs
                 //outputs
                 . data_out   (reg_1[2]            )
                 . data_out   (reg_1[2]            )
                 );
                 );
 
 
assign reg_1[31:3] = 29'h0;
assign reg_1[7:3] = 5'h0;
 
 
 
 
//-----------------------------------------------------------------------
//-----------------------------------------------------------------------
// Logic for Register 2 :  Baud Rate Control
// Logic for Register 2 :  Baud Rate Control
//-----------------------------------------------------------------------
//-----------------------------------------------------------------------
wire [11:0]   cfg_baud_16x    = reg_2[11:0];
wire [11:0]   cfg_baud_16x    = {reg_3[3:0],reg_2[7:0]};
 
 
generic_register #(12,0  ) u_uart_ctrl_reg2 (
generic_register #(8,0  ) u_uart_ctrl_reg2 (
              .we            ({12{sw_wr_en_2 &
              .we            ({8{sw_wr_en_2 &
                                 wr_be[0]   }}  ),
                                 wr_be   }}  ),
              .data_in       (reg_wdata[11:0]    ),
              .data_in       (reg_wdata[7:0]    ),
              .reset_n       (reset_n           ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
              .clk           (mclk              ),
 
 
              //List of Outs
              //List of Outs
              .data_out      (reg_2[11:0]        )
              .data_out      (reg_2[7:0]        )
          );
          );
 
 
 
generic_register #(4,0  ) u_uart_ctrl_reg3 (
 
              .we            ({4{sw_wr_en_3 &
 
                                 wr_be   }}  ),
 
              .data_in       (reg_wdata[3:0]    ),
 
              .reset_n       (reset_n           ),
 
              .clk           (mclk              ),
 
 
assign reg_2[31:12] = 20'h0;
              //List of Outs
 
              .data_out      (reg_3[3:0]        )
 
          );
 
 
 
assign reg_3[7:4] = 4'h0;
 
 
 
 
assign reg_3[31:0] = {30'h0,rx_fifo_empty,tx_fifo_full};
// reg-4  status
 
//
 
assign reg_4[7:0] = {6'h0,rx_fifo_empty,tx_fifo_full};
 
 
// reg_4 is tx_fifo wr
// reg_5 is tx_fifo wr
assign tx_fifo_wr_en  = sw_wr_en_4 & reg_ack;
assign tx_fifo_wr_en  = sw_wr_en_5 & reg_ack & !tx_fifo_full;
assign tx_fifo_data   = reg_wdata[7:0];
assign tx_fifo_data   = reg_wdata[7:0];
 
 
// reg_5 is rx_fifo read
// reg_6 is rx_fifo read
// rx_fifo read data
// rx_fifo read data
assign reg_5[31:0] = {24'h0,rx_fifo_data};
assign reg_6[7:0] = {rx_fifo_data};
assign  rx_fifo_rd_en = sw_rd_en_5 & reg_ack;
assign  rx_fifo_rd_en = sw_rd_en_6 & reg_ack & !rx_fifo_empty;
 
 
 
 
endmodule
endmodule
 
 
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