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Line 12... |
//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Nov 26, 2016 ////
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//// Revision : ////
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//// v-0.0 : Nov 26, 2016 ////
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//// 1. Initial version picked from ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// v-0.1 : Nov 28, 2016 ////
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//// 1. Register access for Read/Write fifo & baudrate ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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Line 62... |
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// Outputs
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// Outputs
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reg_rdata,
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reg_rdata,
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reg_ack,
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reg_ack,
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// Uart Tx fifo interface
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tx_fifo_full,
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tx_fifo_wr_en,
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tx_fifo_data,
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// Uart Rx fifo interface
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rx_fifo_empty,
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rx_fifo_rd_en,
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rx_fifo_data,
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// configuration
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// configuration
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cfg_tx_enable,
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cfg_tx_enable,
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cfg_rx_enable,
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cfg_rx_enable,
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cfg_stop_bit ,
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cfg_stop_bit ,
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cfg_pri_mod ,
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cfg_pri_mod ,
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cfg_baud_16x ,
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frm_error_o,
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frm_error_o,
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par_error_o,
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par_error_o,
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rx_fifo_full_err_o
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rx_fifo_full_err_o
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Line 90... |
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input mclk;
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input mclk;
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input reset_n;
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input reset_n;
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//--------------------------------
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// Uart Tx fifo interface
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//--------------------------------
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input tx_fifo_full;
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output tx_fifo_wr_en;
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output [7:0] tx_fifo_data;
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//--------------------------------
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// Uart Rx fifo interface
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//--------------------------------
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input rx_fifo_empty;
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output rx_fifo_rd_en;
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input [7:0] rx_fifo_data;
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//----------------------------------
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// configuration
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// configuration
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//----------------------------------
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output cfg_tx_enable ; // Tx Enable
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output cfg_tx_enable ; // Tx Enable
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output cfg_rx_enable ; // Rx Enable
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output cfg_rx_enable ; // Rx Enable
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output cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop
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output cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop
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output [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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output [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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output [11:0] cfg_baud_16x ; // 16x Baud clock config
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input frm_error_o ; // framing error
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input frm_error_o ; // framing error
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input par_error_o ; // par error
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input par_error_o ; // par error
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input rx_fifo_full_err_o ; // rx fifo full error
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input rx_fifo_full_err_o ; // rx fifo full error
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Line 333... |
);
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);
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assign reg_1[31:3] = 29'h0;
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assign reg_1[31:3] = 29'h0;
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//-----------------------------------------------------------------------
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// Logic for Register 2 : Baud Rate Control
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//-----------------------------------------------------------------------
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wire [11:0] cfg_baud_16x = reg_2[11:0];
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generic_register #(12,0 ) u_uart_ctrl_reg2 (
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.we ({12{sw_wr_en_2 &
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wr_be[0] }} ),
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.data_in (reg_wdata[11:0] ),
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.reset_n (reset_n ),
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.clk (mclk ),
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//List of Outs
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.data_out (reg_2[11:0] )
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);
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assign reg_2[31:12] = 20'h0;
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assign reg_3[31:0] = {30'h0,rx_fifo_empty,tx_fifo_full};
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// reg_4 is tx_fifo wr
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assign tx_fifo_wr_en = sw_wr_en_4;
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assign tx_fifo_data = reg_wdata[7:0];
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// reg_5 is rx_fifo read
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// rx_fifo read data
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assign reg_5[31:0] = {24'h0,rx_fifo_data};
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assign rx_fifo_rd_en = sw_rd_en_5;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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