URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
[/] [oms8051mini/] [trunk/] [rtl/] [uart/] [uart_core.v] - Diff between revs 6 and 11
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 6 |
Rev 11 |
| Line 12... |
Line 12... |
//// nothing ////
|
//// nothing ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// ////
|
//// ////
|
//// Revision : ////
|
//////////////////////////////////////////////////////////////////////
|
//// v-0.0 : NOV 26, 2016 ////
|
//// Revision :
|
//// 1. initial version picked from ////
|
//// v-0.0 : NOV 26, 2016
|
//// http://www.opencores.org/cores/turbo8051/ ////
|
//// 1. initial version picked from
|
//// v-0.1 : NOV 28, 2016 ////
|
//// http://www.opencores.org/cores/turbo8051/
|
//// 2. Register access correction ////
|
//// v-0.1 : NOV 28, 2016
|
//// ////
|
//// 1. Register access correction
|
|
//// v-0.2 : NOV 28, 2016
|
|
//// 1. Register access changed from 32 bit to 8bit
|
|
////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
| Line 94... |
Line 97... |
// Reg Bus Interface Signal
|
// Reg Bus Interface Signal
|
//---------------------------------
|
//---------------------------------
|
input reg_cs ;
|
input reg_cs ;
|
input reg_wr ;
|
input reg_wr ;
|
input [3:0] reg_addr ;
|
input [3:0] reg_addr ;
|
input [31:0] reg_wdata ;
|
input [7:0] reg_wdata ;
|
input [3:0] reg_be ;
|
input reg_be ;
|
|
|
// Outputs
|
// Outputs
|
output [31:0] reg_rdata ;
|
output [7:0] reg_rdata ;
|
output reg_ack ;
|
output reg_ack ;
|
|
|
// Line Interface
|
// Line Interface
|
input si ; // uart si
|
input si ; // uart si
|
output so ; // uart so
|
output so ; // uart so
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.