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Line 12... |
//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Nov 26, 2016 ////
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//// Revision : ////
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//// v-0.0 : NOV 26, 2016 ////
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//// 1. initial version picked from ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// v-0.1 : NOV 28, 2016 ////
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//// 2. Register access correction ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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Line 48... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module uart_core
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module uart_core
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(
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(
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line_reset_n ,
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line_clk_16x ,
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app_reset_n ,
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app_reset_n ,
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app_clk ,
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app_clk ,
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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| Line 82... |
Line 85... |
(DP == 128) ? 7 :
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(DP == 128) ? 7 :
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(DP == 256) ? 8 : 0;
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(DP == 256) ? 8 : 0;
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input line_reset_n ; // line reset
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input line_clk_16x ; // line clock
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input app_reset_n ; // application reset
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input app_reset_n ; // application reset
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input app_clk ; // application clock
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input app_clk ; // application clock
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//---------------------------------
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//---------------------------------
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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| Line 109... |
Line 109... |
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// Wire Declaration
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// Wire Declaration
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wire [W-1: 0] tx_fifo_rd_data;
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wire [W-1: 0] tx_fifo_rd_data;
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wire [W-1: 0] rx_fifo_wr_data;
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wire [W-1: 0] rx_fifo_wr_data;
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wire [W-1: 0] app_rxfifo_rddata;
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wire [W-1: 0] app_rxfifo_data;
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wire [W-1: 0] app_txfifo_data;
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wire [1 : 0] error_ind;
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wire [1 : 0] error_ind;
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// Wire
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// Wire
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wire cfg_tx_enable ; // Tx Enable
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wire cfg_tx_enable ; // Tx Enable
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wire cfg_rx_enable ; // Rx Enable
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wire cfg_rx_enable ; // Rx Enable
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| Line 121... |
Line 122... |
wire [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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wire [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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wire frm_error_o ; // framing error
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wire frm_error_o ; // framing error
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wire par_error_o ; // par error
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wire par_error_o ; // par error
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wire rx_fifo_full_err_o ; // rx fifo full error
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wire rx_fifo_full_err_o ; // rx fifo full error
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wire [11:0] cfg_baud_16x ; // 16x Baud clock generation
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wire rx_fifo_wr_full ;
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wire rx_fifo_wr_full ;
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wire app_rxfifo_empty ;
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wire app_rxfifo_empty ;
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uart_cfg u_cfg (
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uart_cfg u_cfg (
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| Line 148... |
Line 151... |
. cfg_tx_enable (cfg_tx_enable),
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. cfg_tx_enable (cfg_tx_enable),
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. cfg_rx_enable (cfg_rx_enable),
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. cfg_rx_enable (cfg_rx_enable),
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. cfg_stop_bit (cfg_stop_bit),
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. cfg_stop_bit (cfg_stop_bit),
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. cfg_pri_mod (cfg_pri_mod),
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. cfg_pri_mod (cfg_pri_mod),
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. cfg_baud_16x (cfg_baud_16x),
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. tx_fifo_full (app_tx_fifo_full),
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. tx_fifo_wr_en (tx_fifo_wr_en),
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. tx_fifo_data (app_txfifo_data),
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. rx_fifo_empty (app_rxfifo_empty),
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. rx_fifo_rd_en (app_rxfifo_rd_en),
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. rx_fifo_data (app_rxfifo_data) ,
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. frm_error_o (frm_error_o),
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. frm_error_o (frm_error_o),
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. par_error_o (par_error_o),
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. par_error_o (par_error_o),
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. rx_fifo_full_err_o (rx_fifo_full_err_o)
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. rx_fifo_full_err_o (rx_fifo_full_err_o)
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);
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);
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// 16x Baud clock generation
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// Example: to generate 19200 Baud clock from 50Mhz Link clock
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// 50 * 1000 * 1000 / (2 + cfg_baud_16x) = 19200 * 16
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// cfg_baud_16x = 0xA0 (160)
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wire line_clk_16x;
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clk_ctl #(11) u_clk_ctl (
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// Outputs
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.clk_o (line_clk_16x),
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// Inputs
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.mclk (app_clk),
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.reset_n (app_reset_n),
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.clk_div_ratio (cfg_baud_16x)
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);
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wire line_reset_n = app_reset_n; // todo-> create synchronised reset w.r.t line clock
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uart_txfsm u_txfsm (
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uart_txfsm u_txfsm (
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. reset_n ( line_reset_n ),
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. reset_n ( line_reset_n ),
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. baud_clk_16x ( line_clk_16x ),
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. baud_clk_16x ( line_clk_16x ),
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| Line 205... |
Line 235... |
.full (rx_fifo_wr_full ), // sync'ed to wr_clk
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.full (rx_fifo_wr_full ), // sync'ed to wr_clk
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.wr_total_free_space( ),
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.wr_total_free_space( ),
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.rd_clk (app_clk ),
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.rd_clk (app_clk ),
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.rd_reset_n (app_reset_n ),
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.rd_reset_n (app_reset_n ),
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.rd_en (!app_rxfifo_empty ),
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.rd_en (app_rxfifo_rd_en ),
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.empty (app_rxfifo_empty ), // sync'ed to rd_clk
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.empty (app_rxfifo_empty ), // sync'ed to rd_clk
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.rd_total_aval ( ),
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.rd_total_aval ( ),
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.rd_data (app_rxfifo_rddata )
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.rd_data (app_rxfifo_data )
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);
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);
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async_fifo #(W,DP,0,0) u_txfifo (
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async_fifo #(W,DP,0,0) u_txfifo (
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.wr_clk (app_clk ),
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.wr_clk (app_clk ),
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.wr_reset_n (app_reset_n ),
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.wr_reset_n (app_reset_n ),
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.wr_en (!app_rxfifo_empty ),
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.wr_en (tx_fifo_wr_en ),
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.wr_data (app_rxfifo_rddata ),
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.wr_data (app_txfifo_data ),
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.full ( ), // sync'ed to wr_clk
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.full (app_tx_fifo_full ), // sync'ed to wr_clk
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.wr_total_free_space( ),
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.wr_total_free_space( ),
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.rd_clk (line_clk_16x ),
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.rd_clk (line_clk_16x ),
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.rd_reset_n (line_reset_n ),
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.rd_reset_n (line_reset_n ),
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.rd_en (tx_fifo_rd ),
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.rd_en (tx_fifo_rd ),
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