| Line 30... |
Line 30... |
reg [31:0] read_data;
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reg [31:0] read_data;
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begin
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begin
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@(posedge tb_top.app_clk)
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@(posedge tb_top.app_clk)
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{datain,24'h0});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{datain,24'h0});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
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spi_chip_no[1:0],
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spi_chip_no[1:0],
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2'b0, // Write Operatopm
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2'b0, // Write Operatopm
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2'b0, // Single Transfer
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2'b0, // Single Transfer
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6'h10, // sck clock period
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8'h10, // sck clock period
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5'h2, // cs setup/hold period
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8'h2, // cs setup/hold period
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8'h40 }); // cs bit information
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8'h40 }); // cs bit information
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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while(read_data[31]) begin
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while(read_data[31]) begin
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@(posedge tb_top.app_clk) ;
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@(posedge tb_top.app_clk) ;
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| Line 54... |
Line 54... |
input [7:0] cs_byte;
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input [7:0] cs_byte;
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reg [31:0] read_data;
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reg [31:0] read_data;
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begin
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begin
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@(posedge tb_top.app_clk)
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@(posedge tb_top.app_clk)
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{cmd});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{cmd});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
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spi_chip_no[1:0],
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spi_chip_no[1:0],
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2'b0, // Write Operatopm
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2'b0, // Write Operatopm
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2'h3, // 4 Transfer
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2'h3, // 4 Transfer
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6'h10, // sck clock period
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8'h10, // sck clock period
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5'h2, // cs setup/hold period
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8'h2, // cs setup/hold period
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cs_byte[7:0] }); // cs bit information
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cs_byte[7:0] }); // cs bit information
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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while(read_data[31]) begin
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while(read_data[31]) begin
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@(posedge tb_top.app_clk) ;
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@(posedge tb_top.app_clk) ;
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| Line 79... |
Line 79... |
input [7:0] cs_byte;
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input [7:0] cs_byte;
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reg [31:0] read_data;
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reg [31:0] read_data;
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begin
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begin
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@(posedge tb_top.app_clk)
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@(posedge tb_top.app_clk)
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
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spi_chip_no[1:0],
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spi_chip_no[1:0],
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2'b1, // Read Operatopm
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2'b1, // Read Operatopm
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2'h3, // 4 Transfer
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2'h3, // 4 Transfer
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6'h10, // sck clock period
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8'h10, // sck clock period
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5'h2, // cs setup/hold period
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8'h2, // cs setup/hold period
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cs_byte[7:0] }); // cs bit information
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cs_byte[7:0] }); // cs bit information
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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while(read_data[31]) begin
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while(read_data[31]) begin
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| Line 108... |
Line 108... |
reg [31:0] read_data;
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reg [31:0] read_data;
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begin
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begin
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@(posedge tb_top.app_clk) ;
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@(posedge tb_top.app_clk) ;
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'hD8,address[23:0]});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'hD8,address[23:0]});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
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spi_chip_no[1:0],
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spi_chip_no[1:0],
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2'b0, // Write Operatopm
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2'b0, // Write Operatopm
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2'h3, // 4 Transfer
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2'h3, // 4 Transfer
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6'h10, // sck clock period
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8'h10, // sck clock period
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5'h2, // cs setup/hold period
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8'h2, // cs setup/hold period
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8'h1 }); // cs bit information
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8'h1 }); // cs bit information
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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$display("%t : %m : Sending Sector Errase for Address : %x",$time,address);
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$display("%t : %m : Sending Sector Errase for Address : %x",$time,address);
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| Line 229... |
Line 229... |
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exit_flag = 1;
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exit_flag = 1;
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while(exit_flag == 1) begin
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while(exit_flag == 1) begin
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'h05,24'h0});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'h05,24'h0});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
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spi_chip_no[1:0],
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spi_chip_no[1:0],
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2'b0, // Write Operation
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2'b0, // Write Operation
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2'b0, // 1 Transfer
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2'b0, // 1 Transfer
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6'h10, // sck clock period
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8'h10, // sck clock period
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5'h2, // cs setup/hold period
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8'h2, // cs setup/hold period
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8'h0 }); // cs bit information
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8'h0 }); // cs bit information
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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while(read_data[31]) begin
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while(read_data[31]) begin
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| Line 247... |
Line 247... |
end
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end
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// Send Status Request Cmd
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// Send Status Request Cmd
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
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spi_chip_no[1:0],
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spi_chip_no[1:0],
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2'b1, // Read Operation
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2'b1, // Read Operation
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2'b0, // 1 Transfer
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2'b0, // 1 Transfer
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6'h10, // sck clock period
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8'h10, // sck clock period
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5'h2, // cs setup/hold period
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8'h2, // cs setup/hold period
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8'h40 }); // cs bit information
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8'h40 }); // cs bit information
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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while(read_data[31]) begin
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while(read_data[31]) begin
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