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[/] [oms8051mini/] [trunk/] [verif/] [agents/] [uart/] [uart_agent.v] - Diff between revs 2 and 7

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Rev 2 Rev 7
Line 1... Line 1...
 
 
 
`include "tb_defines.v"
 
 
module uart_agent (
module uart_agent (
        test_clk,
        test_clk,
        sin,
        sin,
        dsr_n,
        dsr_n,
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reg        test_tx_clk;
reg        test_tx_clk;
reg        stop_err_check;
reg        stop_err_check;
 
 
integer timeout_count;
integer timeout_count;
integer data_bit_number;
integer data_bit_number;
reg [2:0] clk_count;
reg [15:0] clk_count;
 
 
reg      error_ind; // 1 indicate error
reg      error_ind; // 1 indicate error
 
 
initial
initial
begin
begin
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  error_ind = 0;
  error_ind = 0;
end
end
 
 
always @(posedge test_clk)
always @(posedge test_clk)
begin
begin
        if (clk_count == 3'h0)
   if (clk_count == 'h0) begin
                test_tx_clk = ~test_tx_clk;
                test_tx_clk = ~test_tx_clk;
 
      clk_count = control_setup.divisor;
        clk_count = clk_count + 1;
   end else begin
 
      clk_count = clk_count - 1;
 
   end
end
end
assign test_rx_clk = ~test_tx_clk;
assign test_rx_clk = ~test_tx_clk;
 
 
always @(posedge test_clk)
always @(posedge test_clk)
begin
begin
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always @error_detected begin
always @error_detected begin
  error_ind = 1;
  error_ind = 1;
        err_cnt = err_cnt + 1;
        err_cnt = err_cnt + 1;
 
    `TB_GLBL.test_err;
end
end
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
task uart_init;
task uart_init;
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input    [15:0] maxtime;
input    [15:0] maxtime;
input    [15:0] divisor;
input    [15:0] divisor;
input           fifo_enable;
input           fifo_enable;
 
 
begin
begin
 
        clk_count = divisor;
        data_bit_number = data_bit_set + 5;
        data_bit_number = data_bit_set + 5;
end
end
endtask
endtask
 
 
 
 

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