| Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// 8051 external data ram ////
|
//// OMS 8051 Digital core Module ////
|
//// ////
|
//// ////
|
//// This file is part of the 8051 cores project ////
|
//// This file is part of the OMS 8051 cores project ////
|
//// http://www.opencores.org/cores/8051/ ////
|
//// http://www.opencores.org/cores/oms8051mini/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// external data ram ////
|
//// 64K * 8 external data ram ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// nothing ////
|
//// nothing ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Simon Teran, simont@opencores.org ////
|
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
|
//// Revision : Nov 26, 2016 ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// v0.0 - Dinesh A, 8th Dec 2016,
|
|
// 1. converted to 8bit RAM Mode
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
| Line 38... |
Line 43... |
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
|
// CVS Revision History
|
|
//
|
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/10/17 18:53:04 simont
|
|
// added parameter DELAY
|
|
//
|
|
// Revision 1.3 2002/09/30 17:34:01 simont
|
|
// prepared header
|
|
//
|
|
//
|
|
|
|
|
|
module oc8051_xram (clk, rst, wr, be, addr, data_in, data_out, ack, stb);
|
module oc8051_xram (clk, rst, wr, addr, data_in, data_out, ack, stb);
|
//
|
//
|
// external data ram for simulation. part of oc8051_tb
|
// external data ram for simulation. part of oc8051_tb
|
// it's tehnology dependent
|
// it's tehnology dependent
|
//
|
//
|
// clk (in) clock
|
// clk (in) clock
|
| Line 69... |
Line 63... |
|
|
parameter DELAY=1;
|
parameter DELAY=1;
|
|
|
|
|
input clk, wr, stb, rst;
|
input clk, wr, stb, rst;
|
input [3:0] be; // byte enable
|
input [7:0] data_in;
|
input [31:0] data_in;
|
|
input [15:0] addr;
|
input [15:0] addr;
|
output [31:0] data_out;
|
output [7:0] data_out;
|
output ack;
|
output ack;
|
|
|
reg ackw, ackr;
|
reg ackw, ackr;
|
reg [31:0] data_out;
|
reg [7:0] data_out;
|
reg [2:0] cnt;
|
reg [2:0] cnt;
|
integer i;
|
integer i;
|
//
|
//
|
// buffer
|
// buffer
|
reg [7:0] buff [65535:0]; //64kb
|
reg [7:0] buff [65535:0]; //64kb
|
| Line 102... |
Line 95... |
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
ackw <= #1 1'b0;
|
ackw <= #1 1'b0;
|
else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
|
else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
|
if(be[0]) buff[addr] <= #1 data_in[7:0];
|
buff[addr] <= #1 data_in[7:0];
|
if(be[1]) buff[addr+1] <= #1 data_in[15:8];
|
|
if(be[2]) buff[addr+2] <= #1 data_in[23:16];
|
|
if(be[3]) buff[addr+3] <= #1 data_in[31:24];
|
|
ackw <= #1 1'b1;
|
ackw <= #1 1'b1;
|
end else ackw <= #1 1'b0;
|
end else ackw <= #1 1'b0;
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
ackr <= #1 1'b0;
|
ackr <= #1 1'b0;
|
else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
|
else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
|
data_out <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
|
data_out <= #1 buff [addr];
|
ackr <= #1 1'b1;
|
ackr <= #1 1'b1;
|
end else begin
|
end else begin
|
ackr <= #1 1'b0;
|
ackr <= #1 1'b0;
|
data_out <= #1 8'h00;
|
data_out <= #1 8'h00;
|
end
|
end
|
