URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
[/] [oms8051mini/] [trunk/] [verif/] [run/] [run_modelsim] - Diff between revs 31 and 32
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| Rev 31 |
Rev 32 |
| Line 6... |
Line 6... |
set failedm = 0;
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set failedm = 0;
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set failedi = 0;
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set failedi = 0;
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set all_testsm = 0;
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set all_testsm = 0;
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set all_testsi = 0;
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set all_testsi = 0;
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set misc_tests=(uart_test_1 spi_test_1)
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set misc_tests=(spi_test_1)
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#set misc_tests=( )
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#set misc_tests=( )
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set risc_int_tests=(fib divmul sort gcd cast xram i2cm_burst_wrrd)
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set risc_int_tests=(uart_lb fib divmul sort gcd cast xram i2cm_burst_wrrd)
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#set risc_int_tests=(fib divmul sort gcd cast xram all_instr)
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#set risc_int_tests=(fib divmul sort gcd cast xram all_instr)
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echo " Compiling with MODELSIM "
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echo " Compiling with MODELSIM "
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./compile.modelsim | tee ../log/complie.log
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./compile.modelsim | tee ../log/complie.log
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| Line 88... |
Line 88... |
foreach risc_int_test ($risc_int_tests)
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foreach risc_int_test ($risc_int_tests)
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@ i += 1;
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@ i += 1;
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#echo ""
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#echo ""
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\cp ../testcase/dat/${risc_int_test}.dat ./dat/oc8051_xrom.in
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\cp ../testcase/dat/${risc_int_test}.dat ./dat/oc8051_xrom.in
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vsim -do run.do -c tb_top +INTERNAL_ROM | tee ../log/run.log
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vsim -do run.do -c tb_top +${risc_int_test} +INTERNAL_ROM | tee ../log/run.log
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if ($status != 0) then
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if ($status != 0) then
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cat ../log/run.log
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cat ../log/run.log
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exit
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exit
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else if (`tail ../log/run.log | grep PASSED` == "") then
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else if (`tail ../log/run.log | grep PASSED` == "") then
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echo "### test ${i}: ${risc_int_test} --> FAILED"
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echo "### test ${i}: ${risc_int_test} --> FAILED"
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