| Line 166... |
Line 166... |
. mastermode (master_mode ),
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. mastermode (master_mode ),
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. xtal_clk (xtal_clk ),
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. xtal_clk (xtal_clk ),
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. clkout (app_clk ),
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. clkout (app_clk ),
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. reset_out_n (reset_out_n ),
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. reset_out_n (reset_out_n ),
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. ea_in (ea_in ), // internal ROM
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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. ext_reg_cs (reg_cs ),
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. ext_reg_cs (reg_cs ),
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. ext_reg_tid (reg_id ),
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. ext_reg_tid (reg_id ),
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. ext_reg_wr (reg_wr ),
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. ext_reg_wr (reg_wr ),
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| Line 189... |
Line 190... |
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.spi_sck (spi_sck ),
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.spi_sck (spi_sck ),
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.spi_so (spi_so ),
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.spi_so (spi_so ),
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.spi_si (spi_si ),
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.spi_si (spi_si ),
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.spi_cs_n (spi_cs_n ),
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.spi_cs_n (spi_cs_n )
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// External ROM interface
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.wb_xrom_adr (wb_xrom_adr ),
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.wb_xrom_ack (wb_xrom_ack ),
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.wb_xrom_err (wb_xrom_err ),
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.wb_xrom_wr (wb_xrom_wr ),
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.wb_xrom_rdata (wb_xrom_rdata ),
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.wb_xrom_wdata (wb_xrom_wdata ),
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.wb_xrom_stb (wb_xrom_stb ),
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.wb_xrom_cyc (wb_xrom_cyc ),
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// External RAM interface
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.wb_xram_adr (wb_xram_adr ),
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.wb_xram_ack (wb_xram_ack ),
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.wb_xram_err (wb_xram_err ),
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.wb_xram_wr (wb_xram_wr ),
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.wb_xram_be (wb_xram_be ),
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.wb_xram_rdata (wb_xram_rdata ),
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.wb_xram_wdata (wb_xram_wdata ),
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.wb_xram_stb (wb_xram_stb ),
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.wb_xram_cyc (wb_xram_cyc ),
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.ea_in (ea_in ) // internal ROM
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);
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oc8051_xrom oc8051_xrom1
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(
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.rst ( !reset_n ),
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.clk ( app_clk ),
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.addr ( wb_xrom_adr ),
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.data ( wb_xrom_rdata ),
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.stb_i ( wb_xrom_stb ),
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.cyc_i ( wb_xrom_cyc ),
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.ack_o ( wb_xrom_ack )
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);
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);
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defparam oc8051_xrom1.DELAY = 0;
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//
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// external data ram
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//
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oc8051_xram oc8051_xram1 (
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.clk (app_clk ),
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.rst (!reset_n ),
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.wr (wb_xram_wr ),
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.be (wb_xram_be ),
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.addr (wb_xram_adr ),
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.data_in (wb_xram_wdata ),
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.data_out (wb_xram_rdata ),
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.ack (wb_xram_ack ),
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.stb (wb_xram_stb )
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);
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defparam oc8051_xram1.DELAY = 2;
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uart_agent tb_uart (
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uart_agent tb_uart (
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. test_clk (uart_clk_16x ),
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. test_clk (uart_clk_16x ),
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. sin (si ),
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. sin (si ),
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. dsr_n ( ),
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. dsr_n ( ),
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