OpenCores

Rev 10	Rev 11
Line 108...	Line 108...
`//---------------------------------`	`//---------------------------------`
`reg reg_cs ;`	`reg reg_cs ;`
`reg [3:0] reg_id ;`	`reg [3:0] reg_id ;`
`reg reg_wr ;`	`reg reg_wr ;`
`reg [14:0] reg_addr ;`	`reg [14:0] reg_addr ;`
`reg [31:0] reg_wdata ;`	`reg [7:0] reg_wdata ;`
`reg [3:0] reg_be ;`	`reg reg_be ;`

`// Outputs`	`// Outputs`
`wire [31:0] reg_rdata ;`	`wire [7:0] reg_rdata ;`
`wire reg_ack ;`	`wire reg_ack ;`

`reg master_mode ;`	`reg master_mode ;`
`reg ea_in ; // 1--> Internal Memory`	`reg ea_in ; // 1--> Internal Memory`

Line 128...	Line 128...

`wire clkout ;`	`wire clkout ;`
`wire reset_out_n ;`	`wire reset_out_n ;`

`//----------------------------------------`	`//----------------------------------------`
`// 8051 core ROM related signals`
`//---------------------------------------`
`wire [15:0] wb_xrom_adr ; // instruction address`
`wire wb_xrom_ack ; // instruction acknowlage`
`wire wb_xrom_err ; // instruction error`
`wire wb_xrom_wr ; // instruction error`
`wire [31:0] wb_xrom_rdata ; // rom data input`
`wire [31:0] wb_xrom_wdata ; // rom data input`

`wire wb_xrom_stb ; // instruction strobe`
`wire wb_xrom_cyc ; // instruction cycle`


`//----------------------------------------`
`// 8051 core RAM related signals`
`//---------------------------------------`
`wire [15:0] wb_xram_adr ; // data-ram address`
`wire wb_xram_ack ; // data-ram acknowlage`
`wire wb_xram_err ; // data-ram error`
`wire wb_xram_wr ; // data-ram error`
`wire [3:0] wb_xram_be ; // data-ram error`
`wire [31:0] wb_xram_rdata ; // ram data input`
`wire [31:0] wb_xram_wdata ; // ram data input`

`wire wb_xram_stb ; // data-ram strobe`
`wire wb_xram_cyc ; // data-ram cycle`

`//----------------------------------------`

`digital_core u_core (`	`digital_core u_core (`

`. reset_n (reset_n ),`	`. reset_n (reset_n ),`
`. fastsim_mode (1'b1 ),`	`. fastsim_mode (1'b1 ),`
Line 174...	Line 146...
`. ext_reg_cs (reg_cs ),`	`. ext_reg_cs (reg_cs ),`
`. ext_reg_tid (reg_id ),`	`. ext_reg_tid (reg_id ),`
`. ext_reg_wr (reg_wr ),`	`. ext_reg_wr (reg_wr ),`
`. ext_reg_addr (reg_addr[14:0] ),`	`. ext_reg_addr (reg_addr[14:0] ),`
`. ext_reg_wdata (reg_wdata ),`	`. ext_reg_wdata (reg_wdata ),`
`. ext_reg_be (reg_be ),`

`// Outputs`	`// Outputs`
`. ext_reg_rdata (reg_rdata ),`	`. ext_reg_rdata (reg_rdata ),`
`. ext_reg_ack (reg_ack ),`	`. ext_reg_ack (reg_ack ),`

Line 108...

//---------------------------------

//---------------------------------

reg                reg_cs     ;

reg                reg_cs     ;

reg [3:0]          reg_id     ;

reg [3:0]          reg_id     ;

reg                reg_wr         ;

reg                reg_wr         ;

reg  [14:0]        reg_addr       ;

reg  [14:0]        reg_addr       ;

reg  [31:0]        reg_wdata      ;

reg  [7:0]         reg_wdata     ;

reg  [3:0]         reg_be         ;

reg                reg_be        ;

// Outputs

// Outputs

wire  [31:0]        reg_rdata      ;

wire  [7:0]        reg_rdata     ;

wire                reg_ack        ;

wire                reg_ack        ;

reg                 master_mode   ;

reg                 master_mode   ;

reg                 ea_in   ;   // 1--> Internal Memory

reg                 ea_in   ;   // 1--> Internal Memory

Line 128...

wire         clkout             ;

wire         clkout             ;

wire         reset_out_n        ;

wire         reset_out_n        ;

//----------------------------------------

//----------------------------------------

// 8051 core ROM related signals

//---------------------------------------

wire  [15:0]   wb_xrom_adr       ; // instruction address

wire           wb_xrom_ack       ; // instruction acknowlage

wire           wb_xrom_err       ; // instruction error

wire           wb_xrom_wr        ; // instruction error

wire    [31:0] wb_xrom_rdata     ; // rom data input

wire   [31:0]  wb_xrom_wdata     ; // rom data input

wire           wb_xrom_stb       ; // instruction strobe

wire           wb_xrom_cyc       ; // instruction cycle

//----------------------------------------

// 8051 core RAM related signals

//---------------------------------------

wire   [15:0] wb_xram_adr        ; // data-ram address

wire          wb_xram_ack        ; // data-ram acknowlage

wire          wb_xram_err        ; // data-ram error

wire          wb_xram_wr         ; // data-ram error

wire   [3:0]  wb_xram_be         ; // data-ram error

wire   [31:0] wb_xram_rdata      ; // ram data input

wire   [31:0] wb_xram_wdata      ; // ram data input

wire          wb_xram_stb        ; // data-ram strobe

wire          wb_xram_cyc        ; // data-ram cycle

//----------------------------------------

digital_core  u_core (

digital_core  u_core (

             . reset_n             (reset_n            ),

             . reset_n             (reset_n            ),

             . fastsim_mode        (1'b1               ),

             . fastsim_mode        (1'b1               ),

Line 174...

Line 146...

             . ext_reg_cs          (reg_cs             ),

             . ext_reg_cs          (reg_cs             ),

             . ext_reg_tid         (reg_id             ),

             . ext_reg_tid         (reg_id             ),

             . ext_reg_wr          (reg_wr             ),

             . ext_reg_wr          (reg_wr             ),

             . ext_reg_addr        (reg_addr[14:0]     ),

             . ext_reg_addr        (reg_addr[14:0]     ),

             . ext_reg_wdata       (reg_wdata          ),

             . ext_reg_wdata       (reg_wdata          ),

             . ext_reg_be          (reg_be             ),

            // Outputs

            // Outputs

             . ext_reg_rdata       (reg_rdata          ),

             . ext_reg_rdata       (reg_rdata          ),

             . ext_reg_ack         (reg_ack            ),

             . ext_reg_ack         (reg_ack            ),

Browse

Tools

Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [verif/] [tb/] [tb_top.v] - Diff between revs 10 and 11