| Line 27... |
Line 27... |
generic (
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generic (
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C_OPB_AWIDTH : integer := 32;
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C_OPB_AWIDTH : integer := 32;
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C_OPB_DWIDTH : integer := 32;
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C_OPB_DWIDTH : integer := 32;
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C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_0000";
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C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_0000";
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C_HIGHADDR : std_logic_vector := X"FFFF_00FF";
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C_HIGHADDR : std_logic_vector := X"FFFF_00FF";
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C_SYSRST : std_logic := '1';
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C_SYSRST : std_logic := '1'; -- enable external reset
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C_PHYMODE : std_logic := '1';
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C_PHYMODE : std_logic := '1'; -- phy mode
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C_VENDORID : std_logic_vector(15 downto 0) := X"1234";
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C_VENDORID : std_logic_vector(15 downto 0) := X"1234"; -- VID
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C_PRODUCTID : std_logic_vector(15 downto 0) := X"5678";
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C_PRODUCTID : std_logic_vector(15 downto 0) := X"5678"; -- PID
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C_VERSIONBCD : std_logic_vector(15 downto 0) := X"0200";
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C_VERSIONBCD : std_logic_vector(15 downto 0) := X"0200"; -- device version
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C_SELFPOWERED : boolean := false;
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C_SELFPOWERED : boolean := false; -- self or bus powered
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C_RXBUFSIZE_BITS: integer range 7 to 12 := 10;
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C_RXBUFSIZE_BITS: integer range 7 to 12 := 10; -- size of rx buf (2^10 = 1024 bytes)
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C_TXBUFSIZE_BITS: integer range 7 to 12 := 10
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C_TXBUFSIZE_BITS: integer range 7 to 12 := 10 -- size of tx buf (2^10 = 1024 bytes)
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);
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);
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port (
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port (
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-- Global signals
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-- Global signals
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OPB_Clk : in std_logic;
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OPB_Clk : in std_logic;
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OPB_Rst : in std_logic;
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OPB_Rst : in std_logic;
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| Line 59... |
Line 59... |
|
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-- Interrupt
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-- Interrupt
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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|
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-- USB signals
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-- USB signals
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txdp : out std_logic;
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txdp : out std_logic; -- connect to VPO
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txdn : out std_logic;
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txdn : out std_logic; -- connect to VMO/FSEO
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txoe : out std_logic;
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txoe : out std_logic; -- connect to OE
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rxd : in std_logic;
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rxd : in std_logic; -- connect to RCV
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rxdp : in std_logic;
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rxdp : in std_logic; -- connect to VP
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rxdn : in std_logic
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rxdn : in std_logic -- connect to VM
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);
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);
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|
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end entity OPB_USBLITE;
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end entity OPB_USBLITE;
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|
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library Common_v1_00_a;
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library Common_v1_00_a;
|
