| Line 53... |
Line 53... |
<col class=xl68 width=893 style='mso-width-source:userset;mso-width-alt:32658;
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<col class=xl68 width=893 style='mso-width-source:userset;mso-width-alt:32658;
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width:670pt'>
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width:670pt'>
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<tr height=35 style='height:26.25pt'>
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<tr height=35 style='height:26.25pt'>
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<td height=35 width=185 style='height:26.25pt;width:139pt'></td>
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<td height=35 width=185 style='height:26.25pt;width:139pt'></td>
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<td width=103 style='width:77pt'></td>
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<td width=103 style='width:77pt'></td>
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<td class=xl107 colspan=2 width=954 style='mso-ignore:colspan;width:716pt'>Open8
|
<td class=xl106 colspan=2 width=954 style='mso-ignore:colspan;width:716pt'>Open8
|
CPU Core Generics</td>
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CPU Core Generics</td>
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</tr>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<tr height=20 style='height:15.0pt'>
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<td height=20 colspan=2 style='height:15.0pt;mso-ignore:colspan'></td>
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<td height=20 colspan=2 style='height:15.0pt;mso-ignore:colspan'></td>
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<td class=xl67></td>
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<td class=xl67></td>
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| Line 99... |
Line 99... |
"Stack_Start_Addr" by default. If true, the RSP instruction will
|
"Stack_Start_Addr" by default. If true, the RSP instruction will
|
either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0
|
either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0
|
depending on the status of the PSR_GP4 (PSR_S) flag.</td>
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depending on the status of the PSR_GP4 (PSR_S) flag.</td>
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</tr>
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</tr>
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<tr height=80 style='height:60.0pt'>
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<tr height=80 style='height:60.0pt'>
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<td height=80 class=xl108 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
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<td height=80 class=xl107 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
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<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl107 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl108 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
<td class=xl109 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
true, indexed instructions such as LDX, LDO, STX, STO will automatically
|
true, indexed instructions such as LDX, LDO, STX, STO will automatically
|
increment if an odd register is specified. The effect is similar to a normal
|
post-increment if an odd register is specified. The effect is similar to a
|
indexed instruction followed by an UPP instruction on the same register pair.
|
normal indexed instruction followed by an UPP instruction on the same
|
For example, LDX R5 (or LDX R4++) will result in R0 getting the data stored
|
register pair. For example, LDX R5 (or LDX R4++) will result in R0 getting
|
at the address specified by R5:R4. Afterwards, the register pair R5:R4 will
|
the data stored at the address specified by R5:R4. Afterwards, the register
|
be incremented by 1. If false, specifying either register in a register pair
|
pair R5:R4 will be incremented by 1, possibly setting the PSR_C flag. If
|
will result in normal behavior.</td>
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false, specifying either register in a register pair will result in normal
|
|
behavior.</td>
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</tr>
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</tr>
|
<tr height=60 style='height:45.0pt'>
|
<tr height=60 style='height:45.0pt'>
|
<td height=60 class=xl73 style='height:45.0pt;border-top:none'>BRK_Implements_WAI</td>
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<td height=60 class=xl73 style='height:45.0pt;border-top:none'>BRK_Implements_WAI</td>
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<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
|
| Line 122... |
Line 123... |
instruction was executed, but without triggering an interrupt. This is useful
|
instruction was executed, but without triggering an interrupt. This is useful
|
for pausing the CPU until an interrupt occurs. If false, the BRK instruction
|
for pausing the CPU until an interrupt occurs. If false, the BRK instruction
|
flushes the pipeline and executes an extended (5-clock) NOP cycle.</td>
|
flushes the pipeline and executes an extended (5-clock) NOP cycle.</td>
|
</tr>
|
</tr>
|
<tr height=20 style='height:15.0pt'>
|
<tr height=20 style='height:15.0pt'>
|
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Enable_NMI</td>
|
<td height=20 class=xl107 style='height:15.0pt;border-top:none'>Enable_NMI</td>
|
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl107 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl109 style='border-top:none;border-left:none'>TRUE</td>
|
<td class=xl108 style='border-top:none;border-left:none'>TRUE</td>
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Forces
|
<td class=xl109 width=893 style='border-top:none;border-left:none;width:670pt'>Forces
|
bit 0 of the Interrupt Mask to 1, causing Interrupt 0 to be non-maskable.</td>
|
bit 0 of the Interrupt Mask to 1, causing Interrupt 0 to be non-maskable.</td>
|
</tr>
|
</tr>
|
<tr height=40 style='height:30.0pt'>
|
<tr height=40 style='height:30.0pt'>
|
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Sequential_Interrupts</td>
|
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Sequential_Interrupts</td>
|
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
|
| Line 139... |
Line 140... |
sequential. This potentially blocks interrupt priority by allowing a lower
|
sequential. This potentially blocks interrupt priority by allowing a lower
|
level interrupt to block a higher level interrupt. This can be worked around
|
level interrupt to block a higher level interrupt. This can be worked around
|
by clearing the I-bit in known interruptable ISRs.</td>
|
by clearing the I-bit in known interruptable ISRs.</td>
|
</tr>
|
</tr>
|
<tr height=40 style='height:30.0pt'>
|
<tr height=40 style='height:30.0pt'>
|
<td height=40 class=xl108 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
|
<td height=40 class=xl107 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
|
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl107 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl108 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
<td class=xl109 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
set, preserves the general purpose flags GP_PSR4 (PSR_S) to GP_PSR7 on ISR
|
set, preserves the general purpose flags GP_PSR4 (PSR_S) to GP_PSR7 on ISR
|
exit, allowing them to be persistently set by interrupts. The lower four flag
|
exit, allowing them to be persistently set by interrupts. The lower four flag
|
bits are always restored.</td>
|
bits are always restored.</td>
|
</tr>
|
</tr>
|
<tr height=40 style='height:30.0pt'>
|
<tr height=40 style='height:30.0pt'>
|
| Line 158... |
Line 159... |
can alter internal registers if the I bit is set. Also initializes the CPU to
|
can alter internal registers if the I bit is set. Also initializes the CPU to
|
start with the I-bit set. If set to false, there are no restrictions on these
|
start with the I-bit set. If set to false, there are no restrictions on these
|
instructions.</td>
|
instructions.</td>
|
</tr>
|
</tr>
|
<tr height=20 style='height:15.0pt'>
|
<tr height=20 style='height:15.0pt'>
|
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Unsigned_Index_Offsets</td>
|
<td height=20 class=xl107 style='height:15.0pt;border-top:none'>Unsigned_Index_Offsets</td>
|
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl107 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl108 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Determines
|
<td class=xl109 width=893 style='border-top:none;border-left:none;width:670pt'>Determines
|
whether the offset calculation for LDO/STO is signed or unsigned. Default
|
whether the offset calculation for LDO/STO is signed or unsigned. Default
|
behavior is signed.</td>
|
behavior is signed.</td>
|
</tr>
|
</tr>
|
<tr height=40 style='height:30.0pt'>
|
<tr height=40 style='height:30.0pt'>
|
<td height=40 class=xl108 style='height:30.0pt;border-top:none'>Rotate_Ignores_Carry</td>
|
<td height=40 class=xl107 style='height:30.0pt;border-top:none'>Rotate_Ignores_Carry</td>
|
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl107 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl108 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>By
|
<td class=xl109 width=893 style='border-top:none;border-left:none;width:670pt'>By
|
default, the V8 uRISC processor included the carry in rotations, making them
|
default, the V8 uRISC processor included the carry in rotations, making them
|
effectively 9-bit rotations. This generic modifies the ALU such that the
|
effectively 9-bit rotations. This generic modifies the ALU such that the
|
rotations work as classically defined and do NOT involve, or alter, the carry
|
rotations work as classically defined and do NOT involve, or alter, the carry
|
bit.</td>
|
bit.</td>
|
</tr>
|
</tr>
|
| Line 184... |
Line 185... |
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
|
the initial interrupt mask (note that bit 0 is ignored if Enable_NMI is set
|
the initial interrupt mask (note that bit 0 is ignored if Enable_NMI is set
|
TRUE)</td>
|
TRUE)</td>
|
</tr>
|
</tr>
|
<tr height=20 style='height:15.0pt'>
|
<tr height=20 style='height:15.0pt'>
|
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
|
<td height=20 class=xl107 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
|
<td class=xl108 style='border-top:none;border-left:none'>Real</td>
|
<td class=xl107 style='border-top:none;border-left:none'>Real</td>
|
<td class=xl109 style='border-top:none;border-left:none'>-</td>
|
<td class=xl108 style='border-top:none;border-left:none'>-</td>
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Clock
|
<td class=xl109 width=893 style='border-top:none;border-left:none;width:670pt'>Clock
|
frequency in Hz of the CPU clock. Used to configure the 1Mhz/1uSec tick pulse</td>
|
frequency in Hz of the CPU clock. Used to configure the 1Mhz/1uSec tick pulse</td>
|
</tr>
|
</tr>
|
<![if supportMisalignedColumns]>
|
<![if supportMisalignedColumns]>
|
<tr height=0 style='display:none'>
|
<tr height=0 style='display:none'>
|
<td width=185 style='width:139pt'></td>
|
<td width=185 style='width:139pt'></td>
|
