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-- Copyright (c)2020 Jeremy Seth Henry
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-- VHDL units : em_interface
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-- All rights reserved.
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-- Description: Connects all of the components that comprise the ROMEO/JAGM
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--
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-- ESAF test stimulus controller
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- VHDL Units : open8_cfg
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-- Description: Contains project specific constants to configure an Open8
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-- system
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/16/20 Design Start
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-- Seth Henry 04/16/20 Version block added
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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use work.open8_cfg.all;
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package open8_cfg is
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entity em_interface is
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port(
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-- Master oscillator
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Ext_50M_Osc : in std_logic;
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-- Push buttons
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KEY0 : in std_logic;
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KEY1 : in std_logic;
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-- LED outputs
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LEDS : out std_logic_vector(7 downto 0);
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-- Configuration Switches
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DIPSW : in std_logic_vector(3 downto 0);
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-- GPINs (input only)
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GPIN0 : in std_logic_vector(1 downto 0);
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GPIN1 : in std_logic_vector(1 downto 0);
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GPIN2 : in std_logic_vector(2 downto 0);
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-- GPIO
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GPIO0 : inout std_logic_vector(33 downto 0);
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GPIO1 : inout std_logic_vector(33 downto 0);
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GPIO2 : inout std_logic_vector(12 downto 0)
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);
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end entity;
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architecture behave of em_interface is
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-- I/O mapping aliases
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-- Clocks & Resets
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alias Sys_Clock_50M is Ext_50M_Osc;
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-- External Pushbuttons
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alias FMSIM_PB_Reset is GPIN2(0);
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alias FPGA_PB_Reset is GPIN2(2);
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alias DBG_PB is GPIO2(3);
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-- Diagnostic
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alias JP1_1 is GPIN0(0);
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alias JP1_3 is GPIN0(1);
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alias JP1_37 is GPIO0(30);
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alias JP1_38 is GPIO0(31);
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alias JP1_39 is GPIO0(32);
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alias JP1_40 is GPIO0(33);
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alias JP2_4 is GPIO1(1);
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-- Status LED
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alias Status_LED is GPIO2(10);
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-- Telemetry Serial
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alias TM_Tx_Out is GPIO1(0);
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alias TM_CTS_In is GPIN1(1);
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-- Vector RX (TS Input)
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alias Vec_Rx is GPIN1(0);
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-- MAX 7221 SPI Interface
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alias MX_LDCSn is GPIO2(9);
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alias Mx_Clock is GPIO2(5);
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alias Mx_Data is GPIO2(7);
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-- SDLC Serial Interface
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alias SDLC_EM2IF is GPIO0(18);
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alias SDLC_Clock is GPIO0(19);
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alias SDLC_IF2EM is GPIO0(20);
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-- Relay/Discrete I/O
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alias EM_Elec_Power is GPIO2(8);
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alias EM_Arm_Power is GPIO0(29);
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alias EM_Separation is GPIO0(5);
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alias EM_Detonate_Cmd_1 is GPIO0(17);
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alias EM_Detonate_Cmd_2 is GPIO0(9);
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alias EM_Test_G1 is GPIO0(7);
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alias EM_Test_G2 is GPIO0(11);
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alias EM_Test_Mode is GPIO0(2);
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alias EM_Config_ID_1 is GPIO0(0);
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alias EM_Config_ID_2 is GPIO0(4);
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alias EM_Config_ID_3 is GPIO0(8);
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alias EM_Spare_1 is GPIO0(1);
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alias EM_Int_Impact is GPIO0(3);
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alias EM_FPGA_POR_Reset is GPIO0(6);
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alias EM_PIC_POR_Reset is GPIO0(10);
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alias EM_Spare_Rly is GPIO0(12);
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alias EM_Accel_PDM is GPIO2(11);
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-- Unused EM signals
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alias EM_TXD_TST is GPIO0(13);
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alias EM_Aux_In_1 is GPIO0(14);
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alias EM_Aux_Out_1 is GPIO0(15);
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alias EM_RCV_TST is GPIO0(16);
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-- PC FM Simulator IF (NANO)
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alias PC_Contact is GPIO0(26);
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alias PC_EM2FM is GPIO0(27);
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alias PC_FM2EM is GPIO0(28);
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alias PC_Fire_Out is GPIO0(21);
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-- MC FM Simulator IF (NANO)
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alias MC_Contact is GPIO0(23);
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alias MC_EM2FM is GPIO0(24);
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alias MC_FM2EM is GPIO0(25);
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alias MC_Fire_Out is GPIO0(22);
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-- NI DIO
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alias NI_P0_0 is GPIO1(17);
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alias NI_P0_1 is GPIO1(2);
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alias NI_P0_2 is GPIO1(15);
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alias NI_P0_3 is GPIO1(4);
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alias NI_P0_4 is GPIO1(13);
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alias NI_P0_5 is GPIO1(6);
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alias NI_P0_6 is GPIO1(11);
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alias NI_P0_7 is GPIO1(8);
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alias NI_P1_0 is GPIO1(9);
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alias NI_P1_1 is GPIO1(10);
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alias NI_P1_2 is GPIO1(7);
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alias NI_P1_3 is GPIO1(12);
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alias NI_P1_4 is GPIO1(5);
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alias NI_P1_5 is GPIO1(14);
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alias NI_P1_6 is GPIO1(3);
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alias NI_P1_7 is GPIO1(16);
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alias NI_P2_0 is GPIO1(33);
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alias NI_P2_1 is GPIO1(18);
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alias NI_P2_2 is GPIO1(31);
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alias NI_P2_3 is GPIO1(20);
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alias NI_P2_4 is GPIO1(29);
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alias NI_P2_5 is GPIO1(22);
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alias NI_P2_6 is GPIO1(27);
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alias NI_P2_7 is GPIO1(20);
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alias NI_P3_0 is GPIO1(25);
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alias NI_P3_1 is GPIO1(26);
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alias NI_P3_2 is GPIO1(23);
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alias NI_P3_3 is GPIO1(28);
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alias NI_P3_4 is GPIO1(21);
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alias NI_P3_5 is GPIO1(30);
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alias NI_P3_6 is GPIO1(19);
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alias NI_P3_7 is GPIO1(32);
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-- Internal mapping signals
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signal Sys_Async_Reset : std_logic;
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signal Ext_Switches : DATA_TYPE := x"00";
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signal CPU_Flags : EXT_GP_FLAGS := "00000";
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signal BAR_LED : DATA_TYPE := x"00";
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signal Vec_Req : std_logic := '0';
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signal Vec_Index : std_logic_vector(5 downto 0) := "000000";
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signal Vec_Data : std_logic_vector(15 downto 0 ) := x"0000";
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-- Internal signals & constants
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begin
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constant Clock_Frequency : real := 100000000.0;
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-- Peripheral Options
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-- SDLC Configuration
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Reset_Input_proc: process( Sys_Clock_50M, FPGA_PB_Reset, NI_P0_7 )
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constant Master_Mode : boolean := true;
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constant BitClock_Freq : real := 20000000.0;
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constant Clock_Offset : integer := 3;
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-- FM Serial Configuration
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constant SERIAL_58_125K : real := 58125.0;
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constant PARITY_ENABLE : boolean := true;
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constant PARITY_ODD_EVENn : std_logic := '1';
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-- MAX7221 Driver Configuration
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constant MAX7221_BITRATE : real := 5000000.0;
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-- Test Vector Receiver Configuration
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constant VECTOR_BITRATE : real := 10000000.0;
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constant VECTOR_PARITY : boolean := TRUE;
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constant VECTOR_ODD_EVENn : std_logic := '0';
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-- Open8 CPU Options
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constant Allow_Stack_Address_Move : boolean := true;
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constant Stack_Xfer_Flag : integer := PSR_GP4;
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constant Enable_Auto_Increment : boolean := true;
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constant BRK_Implements_WAI : boolean := true;
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constant Enable_NMI : boolean := true;
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constant Sequential_Interrupts : boolean := true;
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constant RTI_Ignores_GP_Flags : boolean := true;
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constant Default_Int_Mask : DATA_TYPE := x"00";
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-- System Memory Map
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constant RAM_Address : ADDRESS_TYPE := x"0000"; -- System RAM
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constant ALU_Address : ADDRESS_TYPE := x"1000"; -- ALU16 coprocessor
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constant RTC_Address : ADDRESS_TYPE := x"1100"; -- System Timer / RT Clock
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constant ETC_Address : ADDRESS_TYPE := x"1200"; -- Epoch Timer/Alarm Clock
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constant TMR_Address : ADDRESS_TYPE := x"1400"; -- PIT timer
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constant SDLC_Address : ADDRESS_TYPE := x"1800"; -- LCD serial interface
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constant LED_Address : ADDRESS_TYPE := x"2000"; -- LED Display
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constant DSW_Address : ADDRESS_TYPE := x"2100"; -- Dip Switches
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constant BTN_Address : ADDRESS_TYPE := x"2200"; -- Push Buttons
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constant SER_Address : ADDRESS_TYPE := x"2400"; -- UART interface
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constant MAX_Address : ADDRESS_TYPE := x"2800"; -- Max 7221 base address
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constant VEC_Address : ADDRESS_TYPE := x"3000"; -- Vector RX base address
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constant CHR_Address : ADDRESS_TYPE := x"3100"; -- Elapsed Time / Chronometer
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constant ROM_Address : ADDRESS_TYPE := x"8000"; -- Application ROM
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constant ISR_Start_Addr : ADDRESS_TYPE := x"FFF0"; -- ISR Vector Table
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-- RAM size is used to calculate the initial stack pointer, which is set at
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-- the top of the RAM region.
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constant RAM_Size : integer := 4096;
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-- Interrupt assignments
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-- These are assigned in order priority from 0 (highest) to 7 (lowest)
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constant INT_PIT : integer range 0 to OPEN8_DATA_WIDTH - 1 := 0;
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constant INT_ETC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 1;
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constant INT_TMR : integer range 0 to OPEN8_DATA_WIDTH - 1 := 2;
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constant INT_ALU : integer range 0 to OPEN8_DATA_WIDTH - 1 := 3;
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constant INT_RTC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 4;
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constant INT_SDLC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 5;
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constant INT_BTN : integer range 0 to OPEN8_DATA_WIDTH - 1 := 6;
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constant INT_VEC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 7;
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-- Set this to the number of readable modules (entities wth a Rd_Data port) in the design,
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-- as it sets the number of ports on the read aggregator function.
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constant NUM_READ_BUSES : integer := 13;
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-- Read Data Bus aggregator and bus assignments.
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-- Note that the ordering isn't important, only that each device has a
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-- unique number less than READ_BUS_COUNT.
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constant RDB_RAM : integer range 0 to NUM_READ_BUSES - 1 := 0;
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constant RDB_ALU : integer range 0 to NUM_READ_BUSES - 1 := 1;
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constant RDB_RTC : integer range 0 to NUM_READ_BUSES - 1 := 2;
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constant RDB_TMR : integer range 0 to NUM_READ_BUSES - 1 := 3;
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constant RDB_ETC : integer range 0 to NUM_READ_BUSES - 1 := 4;
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constant RDB_LED : integer range 0 to NUM_READ_BUSES - 1 := 5;
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constant RDB_DSW : integer range 0 to NUM_READ_BUSES - 1 := 6;
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constant RDB_BTN : integer range 0 to NUM_READ_BUSES - 1 := 7;
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constant RDB_SDLC : integer range 0 to NUM_READ_BUSES - 1 := 8;
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constant RDB_SER : integer range 0 to NUM_READ_BUSES - 1 := 9;
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constant RDB_VEC : integer range 0 to NUM_READ_BUSES - 1 := 10;
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constant RDB_CHR : integer range 0 to NUM_READ_BUSES - 1 := 11;
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constant RDB_ROM : integer range 0 to NUM_READ_BUSES - 1 := 12;
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-- System configuration calculations - no adjustable parameters below this point
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type OPEN8_BUS_ARRAY is array(0 to NUM_READ_BUSES - 1) of DATA_TYPE;
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constant INIT_READ_BUS : OPEN8_BUS_ARRAY := (others => OPEN8_NULLBUS);
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function merge_buses (x : in OPEN8_BUS_ARRAY) return DATA_TYPE;
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-- Compute the stack start address based on the RAM size
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constant RAM_Vector_Size : integer := ceil_log2(RAM_Size - 1);
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constant RAM_End_Addr : std_logic_vector(RAM_Vector_Size - 1 downto 0)
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:= (others => '1');
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constant Stack_Start_Addr : ADDRESS_TYPE := RAM_Address + RAM_End_Addr;
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end package;
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package body open8_cfg is
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function merge_buses (x : in OPEN8_BUS_ARRAY) return DATA_TYPE is
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variable i : integer := 0;
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variable retval : DATA_TYPE := x"00";
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begin
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begin
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retval := x"00";
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if( FPGA_PB_Reset = '0' or NI_P0_7 = '1' )then
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for i in 0 to NUM_READ_BUSES - 1 loop
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Sys_Async_Reset <= '0';
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retval := retval or x(i);
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elsif( rising_edge( Sys_Clock_50M ) )then
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end loop;
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Sys_Async_Reset <= '1';
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return retval;
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end if;
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end function;
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end process;
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Vec_Req <= NI_P0_6;
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Vec_Index <= NI_P0_5 & NI_P0_4 & NI_P0_3 &
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NI_P0_2 & NI_P0_1 & NI_P0_0;
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Vec_Data <= NI_P2_7 & NI_P2_6 & NI_P2_5 & NI_P2_4 &
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NI_P2_3 & NI_P2_2 & NI_P2_1 & NI_P2_0 &
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NI_P1_7 & NI_P1_6 & NI_P1_5 & NI_P1_4 &
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NI_P1_3 & NI_P1_2 & NI_P1_1 & NI_P1_0;
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NI_P3_0 <= BAR_LED(0);
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NI_P3_1 <= BAR_LED(1);
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NI_P3_2 <= BAR_LED(2);
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NI_P3_3 <= BAR_LED(3);
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NI_P3_4 <= BAR_LED(4);
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NI_P3_5 <= BAR_LED(5);
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NI_P3_6 <= BAR_LED(6);
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NI_P3_7 <= BAR_LED(7);
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LEDS <= BAR_LED;
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Ext_Switches <= DIPSW & KEY1 & KEY0 & DBG_PB & FMSIM_PB_Reset;
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JP1_37 <= CPU_Flags(EXT_ISR);
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JP1_38 <= CPU_Flags(EXT_GP5);
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JP1_39 <= CPU_Flags(EXT_GP6);
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JP1_40 <= CPU_Flags(EXT_GP7);
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U_CORE : entity work.em_core
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port map(
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Sys_Async_Reset => Sys_Async_Reset,
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Sys_Clock_50M => Sys_Clock_50M,
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-- Switches
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Ext_Switches => Ext_Switches,
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-- LEDS
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BAR_LED => BAR_LED,
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Status_LED => Status_LED,
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-- CPU Flags
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CPU_Flags => CPU_Flags,
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-- Telemetry Serial
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TM_Tx_Out => TM_Tx_Out,
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TM_CTS_In => TM_CTS_In,
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-- MAX 7221 SPI Interface
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MX_LDCSn => MX_LDCSn,
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Mx_Clock => Mx_Clock,
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Mx_Data => Mx_Data,
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-- Vector RX (Aux TS Input)
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Vec_Req => Vec_Req,
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Vec_Index => Vec_Index,
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Vec_Data => Vec_Data,
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Vec_Rx => Vec_Rx,
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-- SDLC Serial Interface
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SDLC_EM2IF => SDLC_EM2IF,
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SDLC_Clock => SDLC_Clock,
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SDLC_IF2EM => SDLC_IF2EM,
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-- Relay/Discrete I/O
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EM_Elec_Power => EM_Elec_Power,
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EM_Arm_Power => EM_Arm_Power,
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EM_Separation => EM_Separation,
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EM_Detonate_Cmd_1 => EM_Detonate_Cmd_1,
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EM_Detonate_Cmd_2 => EM_Detonate_Cmd_2,
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EM_Test_G1 => EM_Test_G1,
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EM_Test_G2 => EM_Test_G2,
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EM_Test_Mode => EM_Test_Mode,
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EM_Config_ID_1 => EM_Config_ID_1,
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EM_Config_ID_2 => EM_Config_ID_2,
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EM_Config_ID_3 => EM_Config_ID_3,
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EM_Spare_1 => EM_Spare_1,
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EM_Int_Impact => EM_Int_Impact,
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EM_FPGA_POR_Reset => EM_FPGA_POR_Reset,
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EM_PIC_POR_Reset => EM_PIC_POR_Reset,
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EM_Spare_Rly => EM_Spare_Rly,
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EM_Accel_PDM => EM_Accel_PDM,
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-- PC FM Simulator IF
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PC_Contact => PC_Contact,
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PC_EM2FM => PC_EM2FM,
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PC_FM2EM => PC_FM2EM,
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PC_Fire_Out => PC_Fire_Out,
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-- MC FM Simulator IF
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MC_Contact => MC_Contact,
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MC_EM2FM => MC_EM2FM,
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MC_FM2EM => MC_FM2EM,
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MC_Fire_Out => MC_Fire_Out
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);
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end package body;
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end architecture;
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