| Line 74... |
Line 74... |
Default_Interrupt_Mask : DATA_TYPE := x"FF";
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Default_Interrupt_Mask : DATA_TYPE := x"FF";
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Reset_Level : std_logic := '0' );
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Reset_Level : std_logic := '0' );
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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CPU_Halt : in std_logic;
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Interrupts : in INTERRUPT_BUNDLE;
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Interrupts : in INTERRUPT_BUNDLE;
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Address : out ADDRESS_TYPE;
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Address : out ADDRESS_TYPE;
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Rd_Data : in DATA_TYPE;
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Rd_Data : in DATA_TYPE;
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Rd_Enable : out std_logic;
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Rd_Enable : out std_logic;
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Wr_Data : out DATA_TYPE;
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Wr_Data : out DATA_TYPE;
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| Line 141... |
Line 142... |
constant SOP_GMSK : SUBOP_TYPE := "110";
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constant SOP_GMSK : SUBOP_TYPE := "110";
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constant SOP_JSR : SUBOP_TYPE := "111";
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constant SOP_JSR : SUBOP_TYPE := "111";
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|
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type CPU_STATES is (
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type CPU_STATES is (
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-- Instruction fetch & Decode
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-- Instruction fetch & Decode
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PIPE_FILL_0, PIPE_FILL_1, PIPE_FILL_2, INSTR_DECODE,
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IPF_C0, IPF_C1, IPF_C2, IDC_C0,
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-- Branching
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-- Branching
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BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
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BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
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-- Loads
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-- Loads
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LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
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LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
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LDO_C1, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
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LDO_C1, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
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| Line 154... |
Line 155... |
-- 2-cycle math
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-- 2-cycle math
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MUL_C1, UPP_C1,
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MUL_C1, UPP_C1,
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-- Stack
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-- Stack
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PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
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PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
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-- Subroutines & Interrupts
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-- Subroutines & Interrupts
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WAIT_FOR_INT,
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WAI_Cx, WAH_Cx, BRK_C1,
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ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
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ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
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RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6,
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RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6
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-- Debugging
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);
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BRK_C1 );
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|
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type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
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type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
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CACHE_PREFETCH );
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CACHE_PREFETCH );
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|
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type PC_MODES is ( PC_INCR, PC_LOAD );
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type PC_MODES is ( PC_INCR, PC_LOAD );
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