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[/] [open8_urisc/] [trunk/] [VHDL/] [Open8_pkg.vhd] - Diff between revs 187 and 188

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Rev 187 Rev 188
Line 31... Line 31...
-- Seth Henry      10/29/15 Migrated type/constant definitions to this file
-- Seth Henry      10/29/15 Migrated type/constant definitions to this file
-- Seth Henry      03/09/20 Created new ALU/SP opcodes for handling new RSP
-- Seth Henry      03/09/20 Created new ALU/SP opcodes for handling new RSP
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
--                           the assembler names. Also removed superfluous
--                           the assembler names. Also removed superfluous
--                           signals in the ALU and PC records.
--                           signals in the ALU and PC records.
 
-- Seth Henry      03/17/20 Added new subtype and constants for external
 
--                           GP flags.
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
 
 
Line 57... Line 59...
  subtype ADDRESS_TYPE is std_logic_vector(OPEN8_ADDR_WIDTH - 1 downto 0);
  subtype ADDRESS_TYPE is std_logic_vector(OPEN8_ADDR_WIDTH - 1 downto 0);
  subtype DATA_TYPE    is std_logic_vector(OPEN8_DATA_WIDTH - 1 downto 0);
  subtype DATA_TYPE    is std_logic_vector(OPEN8_DATA_WIDTH - 1 downto 0);
  -- Note: INTERRUPT_BUNDLE must be exactly the same width as DATA_TYPE
  -- Note: INTERRUPT_BUNDLE must be exactly the same width as DATA_TYPE
  subtype INTERRUPT_BUNDLE is DATA_TYPE;
  subtype INTERRUPT_BUNDLE is DATA_TYPE;
 
 
 
  subtype EXT_GP_FLAGS is std_logic_vector(3 downto 0);
 
 
 
  constant EXT_GP4           : integer := 0;
 
  constant EXT_GP5           : integer := 1;
 
  constant EXT_GP6           : integer := 2;
 
  constant EXT_GP7           : integer := 3;
 
 
  -- Component declaration
  -- Component declaration
  --  (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
  --  (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
  component o8_cpu is
  component o8_cpu is
  generic(
  generic(
    Program_Start_Addr       : ADDRESS_TYPE := x"8000";
    Program_Start_Addr       : ADDRESS_TYPE := x"8000";
Line 69... Line 78...
    Allow_Stack_Address_Move : boolean      := false;
    Allow_Stack_Address_Move : boolean      := false;
    Stack_Xfer_Flag          : integer      := 4;
    Stack_Xfer_Flag          : integer      := 4;
    Enable_Auto_Increment    : boolean      := false;
    Enable_Auto_Increment    : boolean      := false;
    BRK_Implements_WAI       : boolean      := false;
    BRK_Implements_WAI       : boolean      := false;
    Enable_NMI               : boolean      := true;
    Enable_NMI               : boolean      := true;
 
    RTI_Ignores_GP_Flags     : boolean      := false;
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";
    Reset_Level              : std_logic    := '0' );
    Reset_Level              : std_logic    := '0' );
  port(
  port(
    Clock                    : in  std_logic;
    Clock                    : in  std_logic;
    Reset                    : in  std_logic;
    Reset                    : in  std_logic;
    CPU_Halt                 : in  std_logic;
    CPU_Halt                 : in  std_logic;
    Interrupts               : in  INTERRUPT_BUNDLE;
    Interrupts               : in  INTERRUPT_BUNDLE;
 
    GP_Flags                 : out EXT_GP_FLAGS;
    Address                  : out ADDRESS_TYPE;
    Address                  : out ADDRESS_TYPE;
    Rd_Data                  : in  DATA_TYPE;
    Rd_Data                  : in  DATA_TYPE;
    Rd_Enable                : out std_logic;
    Rd_Enable                : out std_logic;
    Wr_Data                  : out DATA_TYPE;
    Wr_Data                  : out DATA_TYPE;
    Wr_Enable                : out std_logic );
    Wr_Enable                : out std_logic );

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