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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [Open8_pkg.vhd] - Diff between revs 227 and 228
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| Rev 227 |
Rev 228 |
| Line 76... |
Line 76... |
constant EXT_GP6 : integer := 3;
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constant EXT_GP6 : integer := 3;
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constant EXT_GP7 : integer := 4;
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constant EXT_GP7 : integer := 4;
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constant OPEN8_NULLBUS : DATA_TYPE := x"00";
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constant OPEN8_NULLBUS : DATA_TYPE := x"00";
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constant Reset_Level : std_logic := '1';
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type OPEN8_BUS_TYPE is record
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type OPEN8_BUS_TYPE is record
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Clock : std_logic;
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Clock : std_logic;
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Reset : std_logic;
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Reset : std_logic;
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uSec_Tick : std_logic;
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uSec_Tick : std_logic;
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Address : ADDRESS_TYPE;
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Address : ADDRESS_TYPE;
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| Line 87... |
Line 89... |
Wr_Data : DATA_TYPE;
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Wr_Data : DATA_TYPE;
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Rd_En : std_logic;
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Rd_En : std_logic;
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GP_Flags : EXT_GP_FLAGS;
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GP_Flags : EXT_GP_FLAGS;
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end record;
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end record;
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constant Reset_Level : std_logic := '1';
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constant INIT_OPEN8_BUS : OPEN8_BUS_TYPE := (
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'0', -- Clock
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Reset_Level, -- Reset
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'0', -- uSec_Tick
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x"0000", -- Address
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'0', -- Wr_En
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OPEN8_NULLBUS, -- Wr_Data
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'0', -- Rd_En
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"00000" -- GP_Flags
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);
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-- Component declaration
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-- Component declaration
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-- (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
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-- (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
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component o8_cpu is
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component o8_cpu is
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generic(
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generic(
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