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[/] [open8_urisc/] [trunk/] [VHDL/] [async_ser_rx.vhd] - Diff between revs 208 and 209

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Rev 208 Rev 209
Line 22... Line 22... 
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
--
 
--
 
-- VHDL Units :  async_ser_rx
 
-- VHDL Units :  async_ser_rx
 
-- Description:  Asynchronous receiver wired for 8[N/E/O]1 data. Parity mode
 
-- Description:  Asynchronous receiver wired for 8[N/E/O]1 data. Parity mode
 
--                and bit rate are set with generics.
 
--                and bit rate are set with generics.
 
 
 
--
 
 
 
--
 
 
 
-- Note: The baud rate generator will produce an approximate frequency. The
 
 
 
--        final bit rate should be within +/- 1% of the true bit rate to
 
 
 
--        ensure the receiver can successfully receive. With a sufficiently
 
 
 
--        high core clock, this is generally achievable for common PC serial
 
 
 
--        data rates.
 
 
 
 
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_unsigned.all;
 
use ieee.std_logic_unsigned.all;
 
use ieee.std_logic_arith.all;
 
use ieee.std_logic_arith.all;

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