Subversion Repositories open8_urisc

--

--

-- VHDL Units :  async_ser_rx

-- VHDL Units :  async_ser_rx

-- Description:  Asynchronous receiver wired for 8[N/E/O]1 data. Parity mode

-- Description:  Asynchronous receiver wired for 8[N/E/O]1 data. Parity mode

--                and bit rate are set with generics.

--                and bit rate are set with generics.

--

--

-- Note: The baud rate generator will produce an approximate frequency. The

-- Note: The baud rate generator will produce an approximate frequency. The

--        final bit rate should be within +/- 1% of the true bit rate to

--        final bit rate should be within +/- 1% of the true bit rate to

--        ensure the receiver can successfully receive. With a sufficiently

--        ensure the receiver can successfully receive. With a sufficiently

--        high core clock, this is generally achievable for common PC serial

--        high core clock, this is generally achievable for common PC serial

--        data rates.

--        data rates.

library ieee;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_arith.all;