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[/] [open8_urisc/] [trunk/] [VHDL/] [async_ser_rx.vhd] - Diff between revs 295 and 321

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Rev 295 Rev 321
Line 33... Line 33...
--
--
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      04/14/20 Code cleanup and revision section added
-- Seth Henry      04/14/20 Code cleanup and revision section added
 
-- Seth Henry      06/08/23 Fixed issue where parity flag could get stuck high
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
Line 116... Line 117...
  constant IO_STOP           : std_logic_vector(3 downto 0) := "1001"; -- 9
  constant IO_STOP           : std_logic_vector(3 downto 0) := "1001"; -- 9
  constant IO_DONE           : std_logic_vector(3 downto 0) := "1010"; -- A
  constant IO_DONE           : std_logic_vector(3 downto 0) := "1010"; -- A
 
 
begin
begin
 
 
  Rx_Perr                    <= Rx_PErr_int;
 
 
 
  UART_Regs: process( Clock, Reset )
  UART_Regs: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Rx_In_SR               <= (others => '0');
      Rx_In_SR               <= (others => '0');
      Rx_State               <= IO_IDLE;
      Rx_State               <= IO_IDLE;
      Rx_Baud_Cntr           <= (others => '0');
      Rx_Baud_Cntr           <= (others => '0');
      Rx_Buffer              <= (others => '0');
      Rx_Buffer              <= (others => '0');
      Rx_Parity              <= '0';
      Rx_Parity              <= '0';
      Rx_Data                <= (others => '0');
      Rx_Data                <= (others => '0');
      Rx_Valid               <= '0';
      Rx_Valid               <= '0';
 
      Rx_Perr                <= '0';
      Rx_PErr_int            <= '0';
      Rx_PErr_int            <= '0';
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      Rx_In_SR               <= Rx_In_SR(2 downto 0) & Rx_In;
      Rx_In_SR               <= Rx_In_SR(2 downto 0) & Rx_In;
 
 
      Rx_Valid               <= '0';
      Rx_Valid               <= '0';
 
      Rx_Perr                <= '0';
      case( Rx_State )is
      case( Rx_State )is
        when IO_STRT =>
        when IO_STRT =>
          if( Rx_In_Q = '1' )then
          if( Rx_In_Q = '1' )then
            Rx_State         <= Rx_State + 1;
            Rx_State         <= Rx_State + 1;
          end if;
          end if;
Line 188... Line 189...
          end if;
          end if;
 
 
        when IO_DONE =>
        when IO_DONE =>
          Rx_Data            <= Rx_Buffer;
          Rx_Data            <= Rx_Buffer;
          Rx_Valid           <= not Rx_PErr_int;
          Rx_Valid           <= not Rx_PErr_int;
 
          Rx_Perr            <= Rx_PErr_int;
          Rx_State           <= Rx_State + 1;
          Rx_State           <= Rx_State + 1;
 
 
        when others =>
        when others =>
          Rx_State           <= IO_IDLE;
          Rx_State           <= IO_IDLE;
 
 

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