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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.open8_pkg.all;
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entity async_ser_tx is
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entity async_ser_tx is
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generic(
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generic(
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Reset_Level : std_logic;
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Reset_Level : std_logic;
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Enable_Parity : boolean;
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Enable_Parity : boolean;
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Parity_Odd_Even_n : std_logic;
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Parity_Odd_Even_n : std_logic;
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);
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);
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end entity;
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end entity;
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architecture behave of async_ser_tx is
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architecture behave of async_ser_tx is
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-- The ceil_log2 function returns the minimum register width required to
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-- hold the supplied integer.
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function ceil_log2 (x : in natural) return natural is
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variable retval : natural;
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begin
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retval := 1;
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while ((2**retval) - 1) < x loop
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retval := retval + 1;
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end loop;
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return retval;
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end ceil_log2;
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constant Tick_Base : integer := Clock_Divider - 1;
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constant Tick_Base : integer := Clock_Divider - 1;
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constant Tick_Bits : integer := ceil_log2(Tick_Base);
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constant Tick_Bits : integer := ceil_log2(Tick_Base);
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constant TICK_DIV : std_logic_vector(Tick_Bits - 1 downto 0) :=
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constant TICK_DIV : std_logic_vector(Tick_Bits - 1 downto 0) :=
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conv_std_logic_vector(Tick_Base, Tick_Bits);
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conv_std_logic_vector(Tick_Base, Tick_Bits);
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signal Tick_Cntr : std_logic_vector(Tick_Bits - 1 downto 0);
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signal Tick_Cntr : std_logic_vector(Tick_Bits - 1 downto 0) :=
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signal Tick_Trig : std_logic;
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(others => '0');
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signal Tx_Enable : std_logic;
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signal Tx_Buffer : std_logic_vector(7 downto 0);
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signal Tx_Parity : std_logic;
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signal Tx_State : std_logic_vector(3 downto 0);
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signal Tick_Trig : std_logic := '0';
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signal Tx_Enable : std_logic := '0';
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signal Tx_Buffer : std_logic_vector(7 downto 0) := x"00";
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signal Tx_Parity : std_logic := '0';
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signal Tx_State : std_logic_vector(3 downto 0) := x"0";
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alias Tx_Bit_Sel is Tx_State(2 downto 0);
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alias Tx_Bit_Sel is Tx_State(2 downto 0);
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-- State machine definitions
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-- State machine definitions
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constant IO_RSV0 : std_logic_vector(3 downto 0) := "1011"; -- B
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constant IO_RSV0 : std_logic_vector(3 downto 0) := "1011"; -- B
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constant IO_RSV1 : std_logic_vector(3 downto 0) := "1100"; -- C
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constant IO_RSV1 : std_logic_vector(3 downto 0) := "1100"; -- C
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