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[/] [open8_urisc/] [trunk/] [VHDL/] [async_ser_tx.vhd] - Diff between revs 209 and 215
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| Rev 209 |
Rev 215 |
| Line 51... |
Line 51... |
Tx_Data : in std_logic_vector(7 downto 0);
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Tx_Data : in std_logic_vector(7 downto 0);
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Tx_Valid : in std_logic;
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Tx_Valid : in std_logic;
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--
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--
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Tx_Out : out std_logic;
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Tx_Out : out std_logic;
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Tx_Done : out std_logic
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Tx_Done : out std_logic
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);
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end entity;
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end entity;
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architecture behave of async_ser_tx is
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architecture behave of async_ser_tx is
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-- The ceil_log2 function returns the minimum register width required to
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-- The ceil_log2 function returns the minimum register width required to
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