OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [async_ser_tx.vhd] - Diff between revs 216 and 218

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 216 Rev 218
Line 1... Line 1...
-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry
-- Copyright (c)2006, 2016, 2020 Jeremy Seth Henry
-- All rights reserved.
-- All rights reserved.
--
--
-- Redistribution and use in source and binary forms, with or without
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--     * Redistributions of source code must retain the above copyright
Line 28... Line 28...
-- Note: The baud rate generator will produce an approximate frequency. The
-- Note: The baud rate generator will produce an approximate frequency. The
--        final bit rate should be within +/- 1% of the true bit rate to
--        final bit rate should be within +/- 1% of the true bit rate to
--        ensure the receiver can successfully receive. With a sufficiently
--        ensure the receiver can successfully receive. With a sufficiently
--        high core clock, this is generally achievable for common PC serial
--        high core clock, this is generally achievable for common PC serial
--        data rates.
--        data rates.
 
--
 
-- Revision History
 
-- Author          Date     Change
 
------------------ -------- ---------------------------------------------------
 
-- Seth Henry      04/14/20 Code cleanup and revision section added
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.