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[/] [open8_urisc/] [trunk/] [VHDL/] [async_ser_tx.vhd] - Diff between revs 294 and 295

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Rev 294 Rev 295
Line 33... Line 33...
--
--
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      04/14/20 Code cleanup and revision section added
-- Seth Henry      04/14/20 Code cleanup and revision section added
-- Seth Henry      09/13/21 Fixed inverted parity bit
 
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
Line 147... Line 146...
      Tx_Out                 <= '1';
      Tx_Out                 <= '1';
 
 
      case( Tx_State )is
      case( Tx_State )is
        when IO_IDLE =>
        when IO_IDLE =>
          if( Enable_Parity )then
          if( Enable_Parity )then
            Tx_Parity        <= not Parity_Odd_Even_n;
            Tx_Parity        <= Parity_Odd_Even_n;
          end if;
          end if;
 
 
        when IO_STRT =>
        when IO_STRT =>
          Tx_Out             <= '0';
          Tx_Out             <= '0';
 
 

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